David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
007812dbdc
Moved the ReadDataW register into the datapath.
...
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
4549a9f1c9
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Katherine Parry
f8b76082e4
fpu unpacking unit created
2021-07-14 17:56:49 -04:00
Ross Thompson
ee09fa5f58
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
David Harris
516b710db6
Fixed busybear by restoring InstrValidW needed by testbench
2021-07-13 14:17:36 -04:00
Ross Thompson
2004b2e044
Fixed back to back store issue.
...
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
2021-07-13 12:46:20 -05:00
David Harris
68d1f87101
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
Ross Thompson
6abd23a61d
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
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Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
David Harris
57e1111df3
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
Ross Thompson
549b7b2a62
Merge branch 'main' into bigbadbranch
2021-07-02 11:52:26 -05:00
Katherine Parry
6216bd7172
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
bbracker
4e09793a9a
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
bbracker
aac9b46a1f
changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
2021-06-25 07:18:38 -04:00
Katherine Parry
bc8d660bc5
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
ced5039776
Revert "fixed forwarding"
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This reverts commit 0f4a4a6ade
2021-06-24 17:39:37 -04:00
bbracker
0f4a4a6ade
fixed forwarding
2021-06-24 11:20:21 -04:00
Ross Thompson
6134c22aca
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
David Harris
9dd3857c26
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
bbracker
28abd28b1f
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
Katherine Parry
65eca433b6
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Katherine Parry
03aea055fa
FMV.X.D imperas test passes
2021-05-24 14:44:30 -04:00
Katherine Parry
71e4a10efb
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
535046e494
small synthesis fixes
2021-05-04 15:21:01 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
James E. Stine
9026357350
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Ross Thompson
cdb7d15709
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
2021-03-24 15:56:55 -05:00
Shreya Sanghai
f35d3b39c8
removed unnecesary PC registers in ifu
2021-03-18 16:31:21 -04:00
David Harris
d4e84c58ed
64-bit AMO debugged
2021-03-11 23:18:33 -05:00
David Harris
fe4d288589
Initial untested implementation of AMO instructions
2021-03-11 00:11:31 -05:00
David Harris
bea8ac6d59
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
David Harris
6f4e8b723e
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
0258901865
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
f57096a5d2
Restored to working multiplier after Lab 2
2021-02-25 15:32:43 -05:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
492ec0ee78
Removed multiplier for lab 2
2021-02-17 16:06:16 -05:00
David Harris
a7dd20b388
Multiply instructions working
2021-02-17 15:29:20 -05:00
David Harris
adc5d5bc1a
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
2a80bcf543
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 19:44:43 -05:00
David Harris
756352f129
Minor tweaks
2021-02-02 19:44:37 -05:00
Noah Boorstin
b5f474d9f5
same thing but do that right this time
2021-02-02 21:47:15 +00:00
Noah Boorstin
6dd5c42d55
change undefined syntax in extend.sv
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don't need verilator execption anymore
2021-02-02 21:39:20 +00:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
616830a3f0
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
229bde5953
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
