Ross Thompson 9e40fb072c Merge branch 'tests' into icache-almost-working		2021-04-25 21:25:36 -05:00
..
alu.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
controller.sv	removed unnecesary PC registers in ifu	2021-03-18 16:31:21 -04:00
datapath.sv	Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.	2021-03-24 15:56:55 -05:00
extend.sv	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
forward.sv	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ieu.sv	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
regfile.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
shifter.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00