cvw/wally-pipelined/src/ieu
2021-07-13 13:20:50 -05:00
..
alu.sv Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
controller.sv Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
datapath.sv Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. 2021-07-09 15:16:38 -05:00
extend.sv small synthesis fixes 2021-05-04 15:21:01 -04:00
forward.sv ah merge; I checked and this does pass all of regression except lints 2021-06-25 07:37:06 -04:00
ieu.sv Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
regfile.sv Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
shifter.sv Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00