Github_Repos/cvw
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6,788 Commits 5 Branches 2 Tags 53 MiB
6a88ac28e4
Commit Graph

724 Commits

Author SHA1 Message Date
David Harris
6a88ac28e4 Fixed csr typos 2023-07-02 02:01:40 -07:00
David Harris
96477a4879 Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode 2023-07-02 02:00:27 -07:00
David Harris
e2708534cd Added environment configuration control (menvcfg/senvcfg) of cbo instructions 2023-07-02 01:52:25 -07:00
David Harris
4d1ddd0c91 Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations 2023-07-02 00:34:30 -07:00
David Harris
110dd42cfb improved decoder checking atomic and RW and MW and privileged instructions 2023-07-02 00:02:03 -07:00
David Harris
07cf1dd9da improved decoder checking atomic instructions 2023-07-01 23:10:57 -07:00
David Harris
e05288afd9 Improved instruction decoding for illegal floating-point loads/stores and fences 2023-07-01 22:48:04 -07:00
David Harris
95960620a2 Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
6d31936e89 Added comment to uart LCR to check reset value after updating FPGA. 2023-06-15 15:39:51 -05:00
Ross Thompson
34d1d50b87 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
a55bcad5c1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
David Harris
52ab586a9d Added input gating on FPU 2023-06-15 12:38:33 -07:00
David Harris
524d8e8469 Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
c7d06382b3 Bit manipulation comment cleanup 2023-06-15 12:16:46 -07:00
Ross Thompson
44c72c20e2 Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
David Harris
33ff9766b4 Gated inputs to BMU when inactive to save power and simulation time 2023-06-15 11:56:59 -07:00
Ross Thompson
2fc8080102 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
David Harris
e0b6a2d693 Fixed UART merge conflict 2023-06-15 11:36:37 -07:00
Ross Thompson
e431f90cf3 Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
37c930bb27
Update wallypipelinedsoc.sv 
Program clean up
 2023-06-15 10:39:37 -07:00
Harshini Srinath
fd00067b7f
Update wallypipelinedcore.sv 
Program clean up
 2023-06-15 10:38:38 -07:00
Harshini Srinath
e3f8280ff9
Update cvw.sv 
Program clean up
 2023-06-15 10:29:33 -07:00
Harshini Srinath
e9cfbd95f4
Update uncore.sv 
Program clean up
 2023-06-15 10:23:47 -07:00
Harshini Srinath
5d8e120031
Update uart_apb.sv 
Program clean up
 2023-06-15 10:21:46 -07:00
Harshini Srinath
53ad51ae54
Update uartPC16550D.sv 
Program clean up
 2023-06-15 10:20:29 -07:00
Harshini Srinath
ae165b35f9
Update rom_ahb.sv 
Program clean up
 2023-06-15 10:13:15 -07:00
Harshini Srinath
97917c2a44
Update ram_ahb.sv 
Program clean up
 2023-06-15 10:10:38 -07:00
Harshini Srinath
a9495e8595
Update plic_apb.sv 
Program clean up
 2023-06-15 10:08:16 -07:00
Harshini Srinath
afa0bcdd16
Update gpio_apb.sv 
Program clean up
 2023-06-15 10:04:28 -07:00
Harshini Srinath
83acb77507
Update clint_apb.sv 
Program clean up
 2023-06-15 09:59:11 -07:00
David Harris
380c9e1dde Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-15 07:01:44 -07:00
Ross Thompson
6bb5f32eb9 Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s. 2023-06-14 15:28:58 -05:00
Harshini Srinath
e0a30ecc22
Merge branch 'main' into main 2023-06-14 11:52:45 -07:00
David Harris
fe35f9ecdb Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this. 2023-06-14 09:44:52 -07:00
David Harris
59bf356064 Removed *** from UART code 2023-06-14 08:47:01 -07:00
David Harris
ea805d32ec Removed QEMU from UART 2023-06-14 08:39:01 -07:00
Harshini Srinath
629ccb191f
Update csrs.sv 
Program clean up
 2023-06-13 22:16:43 -07:00
Harshini Srinath
49c84f888f
Update csrm.sv 
Program clean up
 2023-06-13 22:08:06 -07:00
Harshini Srinath
aff15a0a46
Update csrc.sv 
Program clean up
 2023-06-13 21:54:47 -07:00
Harshini Srinath
fb019a736c
Update csr.sv 
Program clean up
 2023-06-13 21:12:49 -07:00
harshini
17724f7832 deleting CodeAligner file 2023-06-13 17:41:37 -07:00
Harshini Srinath
58c617c548
Update ahbapbbridge.sv 
Program clean up
 2023-06-12 20:49:46 -07:00
Harshini Srinath
475e11e03f
Update trap.sv 
Program clean up
 2023-06-12 20:31:44 -07:00
Harshini Srinath
e2af1fabd2
Update privmode.sv 
Program clean up
 2023-06-12 20:27:48 -07:00
Harshini Srinath
ac7043770d
Update privileged.sv 
Program clean up
 2023-06-12 20:26:07 -07:00
Harshini Srinath
5f7fe5619b
Update csru.sv 
Program clean up
 2023-06-12 20:21:55 -07:00
Harshini Srinath
8487a82efd
Update csrsr.sv 
Program clean up
 2023-06-12 20:19:47 -07:00
Harshini Srinath
32ba95a88f
Update csrsr.sv 
Program clean up
 2023-06-12 20:15:29 -07:00
Harshini Srinath
8c902a3ec2
Update csrs.sv 
Program clean up
 2023-06-12 19:53:41 -07:00