Harshini Srinath
5906b5e729
Update csrm.sv
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Program clean up
2023-06-12 19:42:45 -07:00
Harshini Srinath
f7522ad53c
Update csri.sv
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Program clean up
2023-06-12 19:32:04 -07:00
Harshini Srinath
7dc1595ccc
Update csrc.sv
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Program clean up
2023-06-12 19:03:34 -07:00
Harshini Srinath
ba23a90e9d
Update csr.sv
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Program clean up
2023-06-12 18:51:37 -07:00
Harshini Srinath
794d080aa3
Update pmpchecker.sv
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Program clean up
2023-06-12 18:44:36 -07:00
Harshini Srinath
5a7ee9f1c0
Update pmpadrdec.sv
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Program clean up
2023-06-12 18:41:47 -07:00
Harshini Srinath
ed1d80e37b
Update pmachecker.sv
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Program clean up
2023-06-12 18:39:36 -07:00
Harshini Srinath
91836a6cf3
Update mmu.sv
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Program clean up
2023-06-12 18:36:04 -07:00
Harshini Srinath
3e969c84c7
Update hptw.sv
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Program clean up
2023-06-12 18:31:38 -07:00
Harshini Srinath
3a8631854f
Update adrdecs.sv
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Program clean up
2023-06-12 18:22:32 -07:00
Harshini Srinath
ace24cb879
Update adrdec.sv
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Program clean up
2023-06-12 17:28:21 -07:00
Harshini Srinath
be09e66ec4
Update mul.sv
2023-06-12 14:00:37 -07:00
Harshini Srinath
e7ef3d2136
Update mdu.sv
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Program clean up
2023-06-12 13:54:54 -07:00
Harshini Srinath
6ad67a8102
Update div.sv
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Program clean up
2023-06-12 13:47:09 -07:00
Harshini Srinath
c394f22803
Update swbytemask.sv
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Program clean up
2023-06-12 13:37:35 -07:00
Harshini Srinath
8af3079f10
Update subwordwrite.sv
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Program clean up
2023-06-12 13:35:27 -07:00
Harshini Srinath
c72d573e94
Update subwordread.sv
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Program clean up
2023-06-12 13:31:54 -07:00
Harshini Srinath
086e1cb2df
Update lsu.sv
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Program clean up
2023-06-12 13:29:18 -07:00
Harshini Srinath
45fde3082e
Update lrsc.sv
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Program clean up
2023-06-12 13:14:36 -07:00
Harshini Srinath
a0c6000138
Update dtim.sv
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Program clean up
2023-06-12 13:11:24 -07:00
Harshini Srinath
7a3c78a80d
Update atomic.sv
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Program clean up
2023-06-12 13:08:54 -07:00
Harshini Srinath
70b6d01d2e
Update amoalu.sv
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Program clean up
2023-06-12 12:54:50 -07:00
Harshini Srinath
a53cdbd166
Update spill.sv
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Program clean up
2023-06-12 12:50:11 -07:00
Harshini Srinath
7fa3b87275
Update irom.sv
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Program clean up
2023-06-12 12:44:09 -07:00
Harshini Srinath
128e88a7a0
Update ifu.sv
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Program clean up
2023-06-12 12:38:52 -07:00
Harshini Srinath
e2a9e257c7
Update decompress.sv
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Program clean up
2023-06-12 12:27:55 -07:00
Harshini Srinath
a849fa78cb
Update CodeAligner.py
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Program clean up
2023-06-12 12:25:47 -07:00
Harshini Srinath
80289a1b67
Update shifter.sv
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Program clean up
2023-06-12 12:23:45 -07:00
Harshini Srinath
201d61c575
Update regfile.sv
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Program clean up
2023-06-12 12:21:25 -07:00
Harshini Srinath
055e41bc42
Update ieu.sv
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Program clean up
2023-06-12 12:19:04 -07:00
Harshini Srinath
f5a77be56f
Update extend.sv
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Program clean up
2023-06-12 12:15:33 -07:00
Harshini Srinath
1a59222a08
Update datapath.sv
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Program clean up
2023-06-12 12:13:58 -07:00
Ross Thompson
9a1042b0b1
This parameterizes the testbench but does not use the verilator updates or the new testbench.
2023-06-12 11:00:30 -05:00
Ross Thompson
e5bae37b0b
Merge pull request #327 from harshinisrinath1001/main
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Fixed the spacing in the fpu module
2023-06-12 11:53:52 -04:00
Harshini Srinath
ea0199b3a6
Update prioritythermometer.sv
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Program clean up
2023-06-11 19:18:21 -07:00
Harshini Srinath
8951f965fb
Update or_rows.sv
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Program clean up
2023-06-11 19:16:37 -07:00
Harshini Srinath
aec1330986
Update neg.sv
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Program clean up
2023-06-11 19:15:28 -07:00
Harshini Srinath
0a08da2daf
Update counter.sv
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Program clean up
2023-06-11 19:12:57 -07:00
Harshini Srinath
6c76ca1fef
Update adder.sv
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Program clean up
2023-06-11 19:09:18 -07:00
Harshini Srinath
420ee8dad9
Update unpackinput.sv
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Program clean up
2023-06-11 17:09:11 -07:00
Harshini Srinath
7e0dedea19
Update fctrl.sv
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Program clean up
2023-06-11 17:03:29 -07:00
Harshini Srinath
3bc164a4ca
Update fcmp.sv
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Program clean up
2023-06-11 16:54:52 -07:00
Harshini Srinath
74fa15bcb4
Update fsgninj.sv
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Program clean up
2023-06-11 16:52:00 -07:00
Harshini Srinath
2739ea26a7
Update fregfile.sv
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Program clean up
2023-06-11 16:49:20 -07:00
Harshini Srinath
7770f7e79b
Update fpu.sv
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Program clean up
2023-06-11 16:43:31 -07:00
Harshini Srinath
ca170c8b81
Update fhazard.sv
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Program clean up
2023-06-11 16:06:44 -07:00
Harshini Srinath
d9b58c44cf
Update fcvt.sv
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Program clean up
2023-06-11 16:05:14 -07:00
Harshini Srinath
21015c8e4a
Update fcvt.sv
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Program clean up
2023-06-11 15:59:20 -07:00
Ross Thompson
1bf57e3dd1
Merge branch 'verilator'
2023-06-11 15:28:04 -05:00
David Harris
a192214f86
Fixed lint errors, presumably detected by latest version of verilator
2023-06-11 06:48:42 -07:00
David Harris
d5b237e728
Merge pull request #322 from harshinisrinath1001/main
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Fixing spacing for ebu
2023-06-11 06:00:35 -07:00
Harshini Srinath
fb1e5e401f
Update fctrl.sv
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Program clean up
2023-06-10 19:38:50 -07:00
Harshini Srinath
71248a7523
Update fcmp.sv
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Program clean up
2023-06-10 19:35:58 -07:00
Harshini Srinath
db2ac9604a
Update fcmp.sv
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Program clean up
2023-06-10 19:34:58 -07:00
Harshini Srinath
02e8689999
Update fclassify.sv
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Program clean up
2023-06-10 19:30:18 -07:00
Harshini Srinath
61ebfdb55f
Update controllerinput.sv
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Program clean up
2023-06-10 18:26:06 -07:00
Harshini Srinath
a90bbba617
Update ahbinterface.sv
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Program clean up
2023-06-10 18:18:16 -07:00
Harshini Srinath
2f47a6e04f
Program clean up
2023-06-10 18:13:40 -07:00
Ross Thompson
d6681b5342
Merge pull request #319 from davidharrishmc/dev
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Renamed Performance Counter extension
2023-06-09 21:21:45 -04:00
David Harris
b15c5e2a51
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
2023-06-09 14:40:01 -07:00
David Harris
e2e6f6f255
Added named support for Zicntr and Zihpm
2023-06-09 09:35:51 -07:00
Harshini Srinath
107ebf6a3c
Update ebu.sv
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Code clean up
2023-06-09 08:53:27 -07:00
Harshini Srinath
b4e5f43acb
Update subcachelineread.sv
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Code clean up
2023-06-09 08:50:51 -07:00
Harshini Srinath
7475a0eeed
Update cacheway.sv
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Code clean up
2023-06-09 08:48:11 -07:00
Harshini Srinath
fcac659e34
Update cacheLRU.sv
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Code clean up
2023-06-09 08:43:38 -07:00
Harshini Srinath
1f1fcce062
Update cache.sv
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Formatting clean up
2023-06-09 08:39:57 -07:00
Ross Thompson
9bae203d1c
Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger.
2023-06-09 09:28:24 -05:00
David Harris
62a8332c8f
Merge pull request #313 from ross144/main
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Fix extraneous force in testbench which keep btb in reset.
2023-06-06 08:41:34 -07:00
David Harris
df212ce7d8
Merge pull request #312 from ross144/main
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Fixed typo in coremark makefile.
2023-06-06 05:44:22 -07:00
Ross Thompson
822e60bd3d
Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.
2023-06-05 15:42:05 -05:00
James Stine
51d77b0414
Update some spacing to make it look better
2023-06-05 11:03:06 -05:00
Ross Thompson
80cdb02d43
Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.
2023-05-31 16:51:00 -05:00
Ross Thompson
e56497101a
Updated source code to be compatible with verilator 5.011 for lint only.
2023-05-31 10:44:23 -05:00
Ross Thompson
ab91fe7436
Cleanup parameterization for verilator 5.010.
2023-05-31 10:02:34 -05:00
Ross Thompson
3c94c186db
Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt.
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This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state. Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state. When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE. There may still be a remaining bug here if the pipeline is stalled for another reason. However I don't think it is possible by construction. The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
2023-05-30 15:20:24 -05:00
Ross Thompson
903f2f9063
Merge branch 'param-lim-merge'
2023-05-26 16:25:35 -05:00
Ross Thompson
b8474b208e
Uncore is now parameterized.
2023-05-26 16:24:12 -05:00
Ross Thompson
340aac0934
Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
2023-05-26 16:00:14 -05:00
Ross Thompson
e6d25b7f70
Finished fpu parameterization using Lim's method.
2023-05-26 14:40:06 -05:00
Ross Thompson
ef2bb7df93
fdiv is now parameterized using Lim's method.
2023-05-26 14:25:14 -05:00
Ross Thompson
c76eb315bc
Parameterized fpu's unpack and fma using Lim's method.
2023-05-26 14:12:25 -05:00
Ross Thompson
923c00b928
I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.
2023-05-26 13:56:51 -05:00
Ross Thompson
8aba897386
Update top level parameterized. Simulation slowed down to 4.5 minutes.
2023-05-26 12:13:11 -05:00
Ross Thompson
d47951fb51
The privileged unit is parameterized using Lim's method.
2023-05-26 12:03:46 -05:00
Ross Thompson
dd7c7f0a39
Completed LSU parameterization based on Lim's changes.
2023-05-26 11:26:09 -05:00
Ross Thompson
0c2a54540b
Subwordread now parameterized.
2023-05-26 11:22:44 -05:00
Ross Thompson
3765ebfb9f
PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.
2023-05-26 11:06:48 -05:00
Ross Thompson
60bcd3d21a
Progress on LSU.
2023-05-26 10:47:09 -05:00
Ross Thompson
7c364d5a77
Updated mmu's tlb and hptw to use Lim's parameterization.
2023-05-24 18:02:22 -05:00
Ross Thompson
438c955d1c
PM(P/A) checkers parameterized based on Lim's work.
2023-05-24 17:20:55 -05:00
Ross Thompson
febb2442db
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
Ross Thompson
7fc53226ac
MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.
2023-05-24 15:01:35 -05:00
Ross Thompson
8f9151b125
More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.
2023-05-24 14:56:02 -05:00
Ross Thompson
e33db7f9a7
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
Ross Thompson
d3123fc00a
Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.
2023-05-24 14:05:44 -05:00
Ross Thompson
3de3a42f97
Merged changes.
2023-05-24 13:15:52 -05:00
Ross Thompson
b28a75f32a
Updated headers to local branch history predictors.
2023-05-24 12:52:42 -05:00
Ross Thompson
c5aeb08e5c
Trying to figure out why the parameterization slowed down modelsim so much.
2023-05-24 12:44:42 -05:00
Ross Thompson
6163fc29e1
Adds local history predictor.
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Fixes performance counters, but not coremark.
2023-05-23 18:53:46 -05:00
Ross Thompson
1dc7fb567b
Merge branch 'localhistory'
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Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
2023-05-22 10:13:31 -05:00
