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1879 Commits

Author SHA1 Message Date
davidharrishmc
f1c950a5a7 Update decompress.sv 
typo
 2023-01-04 17:01:26 -08:00
Katherine Parry
b6e900185e forgot the normshift module 2023-01-04 10:48:19 -06:00
Katherine Parry
fd3b967496 some commenting fixes, converter optimizations, and moves normshift into postproc 2023-01-03 15:55:30 -06:00
David Harris
9430aebaab Made Q4.k interface to fgen2/4 consistent 2023-01-01 15:06:32 -08:00
David Harris
86a49ec91f Simplified intdiv selection logic to muxes 2023-01-01 14:04:37 -08:00
David Harris
499b52a7f0 Handle special case Int Div/Rem of |A| < |B| in a single cycle 2023-01-01 13:54:01 -08:00
David Harris
c653f1b30f Fixed radix 2 k = 1 lint 2022-12-31 07:01:50 -08:00
David Harris
a69a3e6eee Fixed backward mux in fdivsqrtstage2 2022-12-31 06:55:20 -08:00
David Harris
dc27284b7f Broken commit starting to address radix 2 issues 2022-12-31 06:19:15 -08:00
David Harris
1e150160eb Moved shared config so wally-shared only has values a user would alter 2022-12-31 05:51:42 -08:00
David Harris
f53d1f6e9b fdivsqrt post processing cleanup 2022-12-31 05:45:15 -08:00
David Harris
d63d565616 fdivsqrt post processing major simplification 2022-12-31 05:42:51 -08:00
David Harris
cc11aa15b2 fdivsqrt post processing simplification 2022-12-31 05:37:48 -08:00
David Harris
cf74f9142b fdivsqrt post processing simplification 2022-12-31 05:36:09 -08:00
David Harris
b2593e5cf5 config file, comment, postproc cleanup 2022-12-31 05:20:56 -08:00
Cedar Turek
5988ebb145 removed unnecessary values from shared config. unbroke division 2022-12-30 21:26:55 -08:00
Cedar Turek
02887e5140 simplified initU and UM logic, separated radix2/4 logic 2022-12-30 18:57:07 -08:00
Cedar Turek
bc55cc21ae various formatting fixes and comments 2022-12-30 18:41:40 -08:00
Cedar Turek
71cdc287aa added mux to intdiv result 2022-12-30 18:06:35 -08:00
Cedar Turek
e41273e59c removed unnecessary mdue gating 2022-12-30 17:53:06 -08:00
Cedar Turek
83a3c72d8d took out broken muxes 2022-12-30 15:13:52 -08:00
Cedar Turek
013527d389 various cleanup 2022-12-30 14:31:23 -08:00
Cedar Turek
1f0e713879 Code cleanup 2022-12-30 14:13:33 -08:00
Ross Thompson
634d13b347 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-30 15:04:54 -06:00
Ross Thompson
eed17d0553 Cleanup spill logic. 2022-12-30 14:59:51 -06:00
Ross Thompson
ffa722e648 Signal renames for PC*NextF and SelSpillNextF. 2022-12-30 14:21:20 -06:00
Cedar Turek
33ca4d1c9a commented complicated step/right shift calc 2022-12-30 12:03:10 -08:00
Cedar Turek
d7fc7c93f3 comment cleaning 2022-12-30 11:11:34 -08:00
Cedar Turek
320b1a7a89 Described internal signals of fdivsqrt top 2022-12-30 11:01:02 -08:00
Cedar Turek
dd78eb6484 Commented fdivsqrt module 2022-12-30 10:52:25 -08:00
Ross Thompson
f4a0f3f71f Removed da page fault from spill logic. 2022-12-30 12:51:56 -06:00
Cedar Turek
d19192144b Begin commenting divsqrt 2022-12-30 10:43:02 -08:00
Ross Thompson
190f03e15c Spill only occurs on 32-bit instructions. 2022-12-30 12:41:25 -06:00
Katherine Parry
668c698bb4 removed ethe second bit from fma alignment shift 2022-12-30 12:07:44 -06:00
Ross Thompson
6ac7adbfc4 Modified IROM to return the correct offset when unaligned. 2022-12-30 11:48:40 -06:00
Katherine Parry
8150305919 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-30 09:56:35 -06:00
David Harris
919525ca17 continued simplifying integer division special cases 2022-12-30 07:40:28 -08:00
David Harris
1006305d75 started simplifying integer division special cases 2022-12-30 07:34:26 -08:00
David Harris
6ae25537ea removed duplicate quotient mux 2022-12-30 07:17:38 -08:00
David Harris
1e65bfd058 simplified sign handling mux 2022-12-30 07:10:47 -08:00
David Harris
55f25457c9 Radix 4 divsqrt 2022-12-30 07:01:44 -08:00
David Harris
2c6c3e799d Clean up sqrt preproc 2022-12-30 07:00:48 -08:00
David Harris
27588af00e Clean up sqrt initialization mux 2022-12-30 06:55:20 -08:00
David Harris
802c440254 Reduced size of preproc right shift 2022-12-30 06:47:40 -08:00
David Harris
d2273e7037 fdivsqrtpreproc shift simplification 2022-12-30 06:45:51 -08:00
David Harris
18f19ce44d fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression 2022-12-30 06:40:25 -08:00
David Harris
0ecbb45b78 Fixed register timing failure on SpecialCaseM in fdivsqrt 2022-12-29 21:09:23 -08:00
Ross Thompson
5d844801d2 Fixed problems with changes to ram2p. 2022-12-29 17:13:48 -06:00
Ross Thompson
a76ea1c6aa Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-29 17:07:53 -06:00
Ross Thompson
31ec70029e Re-enabled the branch predictor in rv64gc. 2022-12-29 17:07:50 -06:00
Katherine Parry
e5a76817df minor optimizations and renaming 2022-12-29 15:54:17 -06:00
Katherine Parry
a8021d7571 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-29 12:37:51 -06:00
David Harris
963185fb22 Clean up names and comments in divsqrt 2022-12-29 08:02:44 -08:00
David Harris
103c4b8324 Factored out hardware unique to RV64 and to IDIV 2022-12-29 07:36:26 -08:00
Katherine Parry
b469831b53 one bitt removed from inital lignment shift 2022-12-28 17:46:53 -06:00
Alessandro Maiuolo
aa1201561e added script in pipelined folder to run regressions with all radix/copies configurations 2022-12-28 07:32:35 -08:00
David Harris
a9d7aa568a fdivsqrtfsm conditional on IDIV (fixed typo) 2022-12-27 22:16:48 -08:00
David Harris
5b7e814670 fdivsqrtfsm conditional on IDIV 2022-12-27 22:15:45 -08:00
David Harris
4648fbee76 fdivsqrtfsm conditional on IDIV 2022-12-27 22:14:09 -08:00
Cedar Turek
42d2ca1556 idiv passing radix 2, four copies 2022-12-27 22:11:18 -08:00
Cedar Turek
6d933a88c7 idiv passing radix 2, four copies 2022-12-27 22:10:48 -08:00
David Harris
f16a15e66f Moved IDIV in fdivsqrtfms into generate block 2022-12-27 22:04:50 -08:00
David Harris
3975fd5ed8 Moved IDIV for postproc into generate block 2022-12-27 22:02:14 -08:00
David Harris
62c01d865a Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc 2022-12-27 21:53:00 -08:00
Cedar Turek
00073155c5 Fixed cycles for multiple iterations. 2-copies radix 2 passing regression. 2022-12-27 21:34:27 -08:00
David Harris
17bd0d9d68 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-27 21:30:13 -08:00
David Harris
0a0ca0ae07 cleanup 2022-12-27 21:29:36 -08:00
David Harris
d6aad0f3c3 Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
David Harris
20787964c9 Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
Ross Thompson
5d91434b32 signal name changes in ram2p. 2022-12-27 15:07:01 -06:00
Ross Thompson
2c0f3d2c6c Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-27 15:06:25 -06:00
Ross Thompson
1f42098758 Added about moving decompressed config generate. 2022-12-27 15:04:55 -06:00
David Harris
9544051c1e Removed MDUE from unnecessary places in fdivsqrt 2022-12-27 10:42:40 -08:00
David Harris
c903f8b8b2 fdiv typo 2022-12-27 10:30:42 -08:00
David Harris
ed26850439 Made SqrtE only true on square root so gating with ~MDUE can be removed) 2022-12-27 10:27:07 -08:00
David Harris
f5cc23cae9 Check for non-negative W in int sign handling 2022-12-27 06:35:17 -08:00
Cedar Turek
d41b07aa85 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
Cedar Turek
21b2ea9666 fpu passing idiv tests on rv32gc 1 copy of radix 2! 2022-12-26 21:47:56 -08:00
Cedar Turek
6977b7ceac took out otfc swap. updated postprocessing quotient/remainder logic for int div. 2022-12-26 21:03:56 -08:00
David Harris
add381a09e Fixed early termination for square root 2022-12-26 08:54:57 -08:00
David Harris
71f214df20 Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
David Harris
3eafd2cca1 Removed unused DivSE from FPU 2022-12-26 07:29:19 -08:00
David Harris
214ef40b1c Moved floating-point tests earlier in Wally config 2022-12-25 22:31:20 -08:00
David Harris
0a067d342f Restored missing floating point load/store tests 2022-12-25 22:28:14 -08:00
David Harris
1a7c7a36d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-25 20:12:55 -08:00
Ross Thompson
1d11ff6153 Added missing assignment for no branch predictor mode. 2022-12-24 17:08:29 -06:00
David Harris
ac4797aac4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-24 12:24:38 -08:00
Ross Thompson
b14b71c7a9 Fixed bug with the performance counters not updating. 2022-12-24 14:24:17 -06:00
David Harris
921b5582da ALU cleanup 2022-12-24 07:18:35 -08:00
cturek
ba3aca413c Added A Sign register. Fixed postprocessing logic for postinc and rem calculation. 2022-12-24 06:46:52 +00:00
Ross Thompson
693f32973f Minor optimizations. 2022-12-23 20:11:36 -06:00
Ross Thompson
424012ce97 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-23 19:51:23 -06:00
Katherine Parry
66510f38af reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
f4f68cdd19 Improved comment. 2022-12-23 15:13:15 -06:00
Ross Thompson
b5a85b55f1 Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
c9c83ca5ae Removed XEnE, YEnE, and ZEnE from forward logic. 
Cleanup comments.
 2022-12-23 14:27:03 -06:00
Ross Thompson
deee433d07 Cleanup floating point hazard logic. 2022-12-23 14:21:47 -06:00
Ross Thompson
c8a0e7685a DON'T USE. First commit in attempt to move fpustall detection into the decode stage. 2022-12-23 12:47:18 -06:00
Ross Thompson
b1aa370ff1 Removed ZForwardEnE and replaced with ZEnE. 
Similar for YForwardEnE.
 2022-12-23 12:27:51 -06:00
Ross Thompson
30dd86d146 Removed unnecessary stall when MatchDE was driven 1 by RdE == 0. 2022-12-23 11:45:42 -06:00