Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-01 17:34:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

various cleanup

Browse Source
This commit is contained in:
Cedar Turek 2022-12-30 14:31:23 -08:00
parent 1f0e713879
commit 013527d389
4 changed files with 23 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
View File

@ -56,7 +56,7 @@ module fdivsqrtfsm(
logic [`DURLEN-1:0] step;
logic [`DURLEN-1:0] cycles;
logic SpecialCaseE, FSpecialCaseE, ISpecialCaseE;
logic SpecialCaseE, FSpecialCaseE;
// FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division
assign IFDivStartE = (FDivStartE | (IDivStartE & `IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
@ -65,10 +65,8 @@ module fdivsqrtfsm(
// terminate immediately on special cases
assign FSpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
if (`IDIV_ON_FPU) begin
assign ISpecialCaseE = AZeroE | BZeroE; // *** why is AZeroE part of this. Should other special cases be considered?
assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE;
end else assign SpecialCaseE = FSpecialCaseE;
if (`IDIV_ON_FPU) assign SpecialCaseE = MDUE ? BZeroE : FSpecialCaseE;
else assign SpecialCaseE = FSpecialCaseE;
flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
// DIVN = `NF+3
@ -117,9 +115,9 @@ module fdivsqrtfsm(
end else if (IFDivStartE) begin
step <= cycles;
if (SpecialCaseE) state <= #1 DONE;
else state <= #1 BUSY;
else state <= #1 BUSY;
end else if (state == BUSY) begin
if (step == 1 | WZeroE) state <= #1 DONE; // finished steps or terminate early on zero residual
if (step == 1 | WZeroE) state <= #1 DONE; // finished steps or terminate early on zero residual
step <= step - 1;
end else if (state == DONE) begin
if (StallM) state <= #1 DONE;

14
pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
View File

@ -77,12 +77,18 @@ module fdivsqrtiter(
// UOTFC Result U and UM registers/initialization mux
// Initialize U to 1.0 and UM to 0 for square root or negative-result int division; U to 0 and UM to -1 otherwise
assign initU = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0;
assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}};
mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, IFDivStartE, UMux);
mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux);
flopen #(`DIVb+1) UReg(clk, IFDivStartE|FDivBusyE, UMux, U[0]);
flopen #(`DIVb+1) UMReg(clk, IFDivStartE|FDivBusyE, UMMux, UM[0]);
/*
mux2 #(`DIVb+1) initUmux(0, {1'b1, {(`DIVb){1'b0}}}, SqrtE, initU);
mux2 #(`DIVb+1) initUMmux({1'b1, {(`DIVb){1'b0}}}, 0, SqrtE, initUM);
*/
mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, IFDivStartE, UMux);
mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux);
flopen #(`DIVb+1) UReg(clk, IFDivStartE|FDivBusyE, UMux, U[0]);
flopen #(`DIVb+1) UMReg(clk, IFDivStartE|FDivBusyE, UMMux, UM[0]);
// C register/initialization mux
// Initialize C to -1 for sqrt and -R for division

15
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
View File

@ -96,11 +96,10 @@ module fdivsqrtpostproc(
// Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed.
assign Sum = WC + WS;
assign NegStickyM = Sum[`DIVb+3];
assign PreQmM = NegStickyM ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;
mux2 #(`DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM);// Select U or U-1 depending on negative sticky bit
mux2 #(`DIVb+1) qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
if (`IDIV_ON_FPU) begin
if (`IDIV_ON_FPU) begin // Int supported
logic [`DIVBLEN:0] NormShiftM;
logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM, NormRemDM;
@ -113,14 +112,12 @@ module fdivsqrtpostproc(
// special case logic
always_comb
if (BZeroM) begin
if (BZeroM) begin // Divide by zero
if (RemOpM) SpecialFPIntDivResultM = AM;
else SpecialFPIntDivResultM = {(`XLEN){1'b1}};
end else if (ALTBM) begin
end else if (ALTBM) begin // Numerator is zero
if (RemOpM) SpecialFPIntDivResultM = AM;
else SpecialFPIntDivResultM = '0;
// IntQuotM = '0;
// IntRemM = {{(`DIVb-`XLEN+4){1'b0}}, AM};
end else begin
logic [`DIVb+3:0] PreIntQuotM;
if (WZeroM) begin
@ -139,7 +136,7 @@ module fdivsqrtpostproc(
if (NegQuotM) IntQuotM = -PreIntQuotM;
else IntQuotM = PreIntQuotM;
if (RemOpM) begin
NormShiftM = ALTBM ? '0 : (mM + (`DIVBLEN+1)'(`DIVa)); // no postshift if forwarding input A to remainder
NormShiftM = ALTBM ? 0 : (mM + (`DIVBLEN+1)'(`DIVa)); // no postshift if forwarding input A to remainder
PreResultM = IntRemM;
end else begin
NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));

4
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
View File

@ -59,7 +59,7 @@ module fdivsqrtpreproc (
logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs
logic NumerZeroE; // Numerator is zero (X or A)
if (`IDIV_ON_FPU) begin
if (`IDIV_ON_FPU) begin // Int Supported
logic signedDiv, NegQuotE;
logic AsBit, BsBit, AsE, BsE, ALTBE;
logic [`XLEN-1:0] AE, BE, PosA, PosB;
@ -127,7 +127,7 @@ module fdivsqrtpreproc (
flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
flopen #(`XLEN) srcareg(clk, IFDivStartE, AE, AM);
end else begin // Int div not supported
end else begin // Int not supported
assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}};
assign IFNormLenD = {Ym, {(`DIVb-`NF-1){1'b0}}};
assign NumerZeroE = XZeroE;