David Harris
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f4f389f373
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Initial version of embench_arch_sweep.py
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2023-11-17 13:27:57 -08:00 |
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David Harris
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70c58a8ce1
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Merge pull request #484 from ross144/main
Changed bpred-sim.py to only simulate 12 jobs at once.
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2023-11-17 13:26:24 -08:00 |
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Rose Thompson
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8cf2c404bf
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bpred-sim only simulates 12 jobs at once.
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2023-11-17 15:21:58 -06:00 |
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David Harris
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8baa5b2e7b
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Merge pull request #483 from ross144/main
Fixed branch predictor embench generation results
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2023-11-17 10:07:30 -08:00 |
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Rose Thompson
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d95d7130a3
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Fixed bugs in paraseHPMC.py
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2023-11-17 12:05:22 -06:00 |
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Rose Thompson
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38b327eaf8
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Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters.
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2023-11-17 11:21:25 -06:00 |
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Jacob Pease
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38cf7f0fb7
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ahbsdc submodule actually added this time.
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2023-11-16 17:46:48 -06:00 |
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Jacob Pease
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9df87872ef
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Deleted vivado-risc-v directory and added ahbsdc.
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2023-11-16 15:13:12 -06:00 |
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Jacob Pease
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23e5fca2a7
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Merge branch 'main' of github.com:jacobpease/cvw
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2023-11-16 14:04:11 -06:00 |
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Jacob Pease
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ff73f798ed
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Replaced vivado-risc-v addins directory with new SDC repo.
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2023-11-16 13:59:12 -06:00 |
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Rose Thompson
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0b49c736b9
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Removed the size opt tests from the branch predictor analysis.
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2023-11-15 22:35:33 -06:00 |
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David Harris
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94201e993f
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Merge pull request #481 from ross144/main
Fixed the BTB logger so sim_bp correctly reports BTB performance
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2023-11-15 17:45:38 -08:00 |
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Rose Thompson
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21b2a71bd6
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Updates to btb logger processing.
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2023-11-15 16:53:44 -06:00 |
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Rose Thompson
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c4f4e0fbc0
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Added btb reference data.
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2023-11-15 16:39:35 -06:00 |
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Rose Thompson
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9a90c15f37
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Extended SeparateBranch to support both just branches and all control flow instructions.
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2023-11-15 16:36:49 -06:00 |
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Rose Thompson
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bc935b1b3b
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Fixed second bug in the logger script when branch logging enabled but counter logger not.
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2023-11-15 14:56:02 -06:00 |
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Rose Thompson
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5d4a89b27c
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Fixed bug in the btb branch logging.
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
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2023-11-15 14:51:47 -06:00 |
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David Harris
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7b2bb86ced
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changed to head of riscv-arch-test
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2023-11-15 09:48:13 -08:00 |
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Rose Thompson
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dc8502899c
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Merge pull request #479 from davidharrishmc/main
Removed and added back in riscv-arch-test to try to fix corruption
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2023-11-15 08:46:42 -08:00 |
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Rose Thompson
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663eb9a17d
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Merge pull request #478 from davidharrishmc/dev
Removed non-functioning Zfh from rv64gc
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2023-11-15 08:46:24 -08:00 |
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David Harris
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eef39bd495
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Fixed typo in lsu parameter
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2023-11-15 08:30:48 -08:00 |
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David Harris
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817ddbc7c5
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Adjusted LSU misaligned buffer to fix synthesis warning
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2023-11-15 08:19:50 -08:00 |
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David Harris
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cfaeeae25a
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Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter
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2023-11-15 08:15:01 -08:00 |
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David Harris
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dc3e412c62
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-15 08:06:35 -08:00 |
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David Harris
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98176665de
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Fixed messed-up hazard.sv
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2023-11-15 08:05:41 -08:00 |
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James E. Stine
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8ca1e3ba37
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missing synth.tcl added for use with wrapper
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2023-11-15 08:48:07 -06:00 |
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James E. Stine
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79d6fe8c93
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Add wrapper passing automatically for individual designs vs. Wally
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2023-11-15 08:45:25 -06:00 |
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David Harris
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20afaa558a
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Added back in riscv-arch-test
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2023-11-15 06:07:57 -08:00 |
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David Harris
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1c4b3e37b1
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Removed riscv-arch-test submodule that was corrupted
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2023-11-15 06:05:55 -08:00 |
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David Harris
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90cf128349
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Added back riscv-arch-test fresh
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2023-11-15 05:48:33 -08:00 |
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David Harris
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18c29dd7d0
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Removed riscv-arch-test submodule that appears corrupted
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2023-11-15 05:46:38 -08:00 |
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David Harris
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3308550409
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-14 19:14:03 -08:00 |
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David Harris
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77338435ce
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Merge pull request #476 from naichewa/main
Final SPI code review
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2023-11-14 19:10:00 -08:00 |
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David Harris
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fb135c957c
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-14 15:19:22 -08:00 |
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David Harris
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5e9157244b
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Restored Zfh to 0 for rv64gc because it breaks floating-point tests
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2023-11-14 15:18:16 -08:00 |
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naichewa
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8ffce456bd
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Merge branch 'spi' into main
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2023-11-14 14:51:06 -08:00 |
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naichewa
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1ab7c926ea
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Final Code Review
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2023-11-14 13:44:59 -08:00 |
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Rose Thompson
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feb45b9b59
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Patched up linux imperas testbench.
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2023-11-14 14:20:13 -06:00 |
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Rose Thompson
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bf51948616
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Merge pull request #474 from davidharrishmc/dev
FP and synthesis cleanup
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2023-11-14 12:03:01 -08:00 |
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Rose Thompson
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65356e362a
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-14 13:54:48 -06:00 |
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Rose Thompson
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1c54a5698b
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Modified the device trees to include all the minor extensions.
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2023-11-14 13:54:16 -06:00 |
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David Harris
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8ba0336c6f
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Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e
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2023-11-14 11:01:58 -08:00 |
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Rose Thompson
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efc1d732d8
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Fixed the imperas testbench to be compatible with the config changes.
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2023-11-14 12:57:44 -06:00 |
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David Harris
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5211b3aa85
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Merge pull request #473 from ross144/main
Missed a few files in the last pull request. Removes the fpga config from the linter.
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2023-11-14 10:15:31 -08:00 |
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Rose Thompson
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fdb75203cb
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Added cbop to to rv32gc.
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2023-11-14 10:55:22 -06:00 |
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David Harris
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a77bea9954
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Merge pull request #472 from ross144/main
Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building
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2023-11-14 08:34:06 -08:00 |
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David Harris
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b67b1f5719
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Merge pull request #471 from stineje/main
Fix multitude of issues with plotPPA as well as issue related to Popen issuing too many synthesis
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2023-11-14 05:51:20 -08:00 |
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James E. Stine
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9dce08a743
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minor typo on ppaSynth and ppaAnalyze
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2023-11-14 02:41:44 -06:00 |
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James E. Stine
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c722e2c59d
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fix plotPPA and other excruciatingly painful problems related to using allWidths and causing empty arrays to be used. This generates the normalized/unnormalized plots
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2023-11-14 01:06:14 -06:00 |
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James E. Stine
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6374d1a200
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Modify ppaSynth.py to be able to not issue excess number of operations with Pool command. This is due to the original command using the Popen command, whereas, using the subprocess.call command solves this issue. The relieves the python script from issuing a ton of synthesis commands and using up all the licenses
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2023-11-14 01:04:37 -06:00 |
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