Rose Thompson
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d4bc9da085
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Fixed another bug in the updated script changes.
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2023-11-13 18:12:02 -06:00 |
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Rose Thompson
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919b7cccf1
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-13 18:10:35 -06:00 |
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Rose Thompson
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f8b65f50b0
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Fixed bugs in the updated fpga synthe script.
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2023-11-13 18:10:22 -06:00 |
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Rose Thompson
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05eb5460b4
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Removed fpga config. No longer needed.
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2023-11-13 17:50:29 -06:00 |
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Rose Thompson
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d5f0c15b90
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Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
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2023-11-13 17:48:28 -06:00 |
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Rose Thompson
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95fc5f4a1c
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Towards removing the FPGA config file.
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2023-11-13 17:20:26 -06:00 |
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Rose Thompson
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6b7ff50a84
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Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.
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2023-11-13 16:44:02 -06:00 |
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Rose Thompson
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a6995af91c
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Fixed bug in uncore updates which broke SDC.
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2023-11-13 16:15:23 -06:00 |
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Rose Thompson
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707b0c557c
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Cleanup and optimization of Zicclsm.
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2023-11-13 14:28:22 -06:00 |
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Rose Thompson
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da59cb71a9
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Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.
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2023-11-13 14:12:27 -06:00 |
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Rose Thompson
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540d8d930d
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Cleanup.
Linux makefile
wally tracer. probably reduce some complexity here.
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2023-11-13 14:04:43 -06:00 |
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Rose Thompson
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1f7d91e8e0
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Merge branch 'Zicclsm'
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2023-11-13 13:53:42 -06:00 |
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Rose Thompson
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55bcc4dbc1
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Updates to linux config files for sdc.
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2023-11-13 13:53:23 -06:00 |
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David Harris
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bcb86b210b
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-13 11:25:46 -08:00 |
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David Harris
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18dddb85b5
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Merge pull request #470 from stineje/main
Remove ppa_ prefix and modify ppaAnalyze.py to handle correct vector
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2023-11-13 11:25:38 -08:00 |
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Rose Thompson
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13908ac41c
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Updated buildroot to use kernel 6.6 and added dedicated qemu emulation script.
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2023-11-13 12:36:32 -06:00 |
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Rose Thompson
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cc7a0b211a
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Cleanup.
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2023-11-13 12:35:11 -06:00 |
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James E. Stine
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74056246d4
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Remove ppa_ prefix and modify ppaAnalyze.py to handle correct vector
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2023-11-13 10:02:10 -06:00 |
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David Harris
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121f685fa2
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Removed assign statement inside always block
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2023-11-13 07:23:15 -08:00 |
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David Harris
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0f4f89edfe
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-13 05:34:14 -08:00 |
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David Harris
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62ab604113
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Merge pull request #469 from stineje/main
update ppaAnalyze to analyze correctionly freqSweep
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2023-11-13 05:33:37 -08:00 |
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James E. Stine
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46bfdf5df9
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update ppaAnalyze to analyze correctionly freqSweep
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2023-11-13 02:39:25 -06:00 |
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David Harris
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6363804ba4
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-12 20:24:25 -08:00 |
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David Harris
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c44ae93e22
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DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst
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2023-11-12 20:23:27 -08:00 |
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David Harris
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065f3f3f6d
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DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst
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2023-11-12 20:23:14 -08:00 |
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Rose Thompson
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8235f66af8
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Merge pull request #468 from davidharrishmc/dev
Divider optimization
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2023-11-12 20:05:44 -08:00 |
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David Harris
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571c7d3be4
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Divider cleanup
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2023-11-12 19:41:12 -08:00 |
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David Harris
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f437336540
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Explained sqrt preshifting
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2023-11-12 10:05:54 -08:00 |
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David Harris
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7c50b2c571
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Renamed qsel to uslc and simplified radix2 uslc
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2023-11-12 06:36:57 -08:00 |
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David Harris
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002034845a
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fdivsqrt comment improvements
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2023-11-12 06:15:47 -08:00 |
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Rose Thompson
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4c2a9c7bab
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Merge pull request #467 from davidharrishmc/main
Sanity in FDIVSQRT bit counts
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2023-11-11 16:37:25 -08:00 |
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David Harris
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6ac83c776e
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Cleaned up number of bits in fdivsqrt
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2023-11-11 15:50:06 -08:00 |
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David Harris
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2bf5143163
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Bug fixes related to size of fpdivsqrt bit count and number of cycles
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2023-11-11 05:58:53 -08:00 |
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David Harris
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448ced00c5
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Fixed testbench-fp to reflect signal name changes
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2023-11-11 04:05:34 -08:00 |
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Rose Thompson
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0d6fb879aa
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Merge pull request #466 from stineje/main
Add pap runs for sweep
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2023-11-10 22:25:55 -08:00 |
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Rose Thompson
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3af8e1ff50
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Merge pull request #465 from davidharrishmc/dev
fdivsqrt cleanup
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2023-11-10 22:25:09 -08:00 |
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James E. Stine
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7b79d8edeb
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Update scripts/synth.tcl to add with parameter for width and also checks wrapper to see if running CONFIG=rv32e to run without WIDTH
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2023-11-10 21:10:35 -06:00 |
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James E. Stine
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65e536e401
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Update ppa/ppaSynth.py for sky130 and better sweep parameterization
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2023-11-10 21:07:36 -06:00 |
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James E. Stine
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e1c935bd9b
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Add bestSynths.csv that are the initial values. If this is re-run after ppaAnalysis.py is run, more refinement can be made
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2023-11-10 21:06:24 -06:00 |
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James E. Stine
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91d7790251
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update README for ppaSynth.py
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2023-11-10 21:05:42 -06:00 |
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David Harris
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d5ba8fc5e6
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fdivsqrt parameter cleanup
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2023-11-10 18:33:08 -08:00 |
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David Harris
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3cae2385ab
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Simplified out LOGRK parameter
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2023-11-10 18:19:41 -08:00 |
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David Harris
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7d0d9dcebe
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divider cleanup
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2023-11-10 18:01:13 -08:00 |
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David Harris
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03864642a7
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fdivsqrt cleanup
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2023-11-10 16:42:32 -08:00 |
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David Harris
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c5b12b7331
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-10 16:40:54 -08:00 |
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Rose Thompson
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c8cca8dfb8
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Simplification.
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2023-11-10 18:39:36 -06:00 |
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Rose Thompson
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9dfe421c55
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Yay! Zicclsm passes my regression test now.
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2023-11-10 18:28:51 -06:00 |
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Rose Thompson
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c0e02ae190
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Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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02ab9fe99c
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Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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bd866e1025
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Fixed some more bugs in the Zicclsm signature.
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2023-11-10 17:36:10 -06:00 |
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