Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
7,273 Commits 5 Branches 2 Tags 53 MiB
5dbe869339
Commit Graph

884 Commits

Author SHA1 Message Date
Ross Thompson
1a003019d6 Actually fixed non-power of 2 issue with RAS. 
Added RAS swapping to branch predictor scripts and configurations.
 2023-09-27 12:25:05 -05:00
Ross Thompson
9ec2bfd052 Fixed sutble RAS bug when the stack size was not a power of 2. 2023-09-27 12:00:47 -05:00
Ross Thompson
a910425adf Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-09-14 10:16:54 -05:00
Ross Thompson
7c89154a7f Slight modification to cachefsm. 2023-09-05 14:07:58 -05:00
Ross Thompson
f00df8d121
Merge pull request #407 from davidharrishmc/dev 
initial spill logic improvement
 2023-09-05 13:29:37 -05:00
Ross Thompson
e39fc44efd
Merge pull request #406 from magpyed/cachesim_fix 
Properly gate LRUWriteEn with ~FlushStage
 2023-09-05 11:10:58 -05:00
David Harris
6ab71ffca6 initial spill logic improvement 2023-09-03 04:21:13 -07:00
David Harris
1ced158596 tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker 2023-09-02 12:56:36 -07:00
Limnanthes Serafini
b334e4ff1f Properly gate LRUWriteEn with ~FlushStage 2023-09-01 23:31:02 -07:00
David Harris
98fa3a78dd Improved tlb and controller coverage; fixed exclusions on broken lines 2023-08-31 00:27:47 -07:00
Kevin Kim
e4ed61a2ce
Merge branch 'openhwgroup:main' into synth_wrapper_gen 2023-08-28 09:03:10 -07:00
Kevin Kim
fc25afb3cb make synth integerates wrapper generation and runs synth on wrapper 2023-08-28 09:02:56 -07:00
Ross Thompson
e7becd53d7
Merge pull request #398 from davidharrishmc/dev 
Completed basic tests of svnapot and svpbmt
 2023-08-28 09:10:20 -05:00
David Harris
10549b7787 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
Kevin Kim
9217e1e767 synth works 2023-08-26 21:11:21 -07:00
David Harris
75986d6641 Fixed merge conflict for ZICBOP 2023-08-25 18:41:57 -07:00
David Harris
3721f8347d Preparing to merge with CBO* changes 2023-08-25 18:41:03 -07:00
David Harris
c07ad03f9d Initial implementation of SVNAPOT and SVPBMT does not break regression 2023-08-25 18:33:08 -07:00
David Harris
9f44241d0f Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
David Harris
847c0dd099
Merge pull request #393 from ross144/main 
Implemented and tested CBOZ instruction
 2023-08-24 19:17:38 -07:00
David Harris
d12be1faac
Merge pull request #394 from harshinisrinath1001/main 
Improved testing of csri with priv.S!
 2023-08-24 19:16:50 -07:00
harshinisrinath
49014e61bc Improved testing of csri with priv.S 2023-08-24 18:39:15 -07:00
Ross Thompson
284ff0ab0b Fixed minor performance bug with CBOZ. 2023-08-24 17:08:20 -05:00
Ross Thompson
fbcf6be06d Now have CBOZ instructions working! 2023-08-24 16:47:35 -05:00
David Harris
aad722ffb1 Check for legal SATP mode values 2023-08-24 05:18:04 -07:00
Ross Thompson
e8bc339638 Oups there was a bug in the SATP fix. RV32GC was broken by the changes. 2023-08-23 09:42:46 -05:00
Ross Thompson
d9a001e87a Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-08-23 09:15:13 -05:00
Jacob Pease
0f29587b0b Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP. 2023-08-22 16:25:56 -05:00
Ross Thompson
a899be7deb Fixed bug with the cbo.inval clearing already cleared lines. 2023-08-21 17:51:51 -05:00
Ross Thompson
6337aab757 Fixed issue when with flush miss. 2023-08-18 16:36:13 -05:00
Ross Thompson
e3bb0d2820 Now we have invalidate, clean, and flush working. 2023-08-18 16:32:22 -05:00
Ross Thompson
b9af790b81 Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests. 2023-08-18 15:59:39 -05:00
Ross Thompson
b842fdb863 Might have working cbo clean and flush instructions. 2023-08-18 14:48:21 -05:00
Ross Thompson
8c7eafffad Fixed cbo instruction decode. 2023-08-18 11:32:30 -05:00
Ross Thompson
a14966e516 Updated the hazard logic for CMO operations. 2023-08-17 17:58:49 -05:00
Ross Thompson
bfde4d2c78 Found first bug in CMO implementation. 2023-08-17 16:57:54 -05:00
Ross Thompson
6a8a82d9e8 CMOZ now implemented in the D cache. 2023-08-17 12:46:40 -05:00
Ross Thompson
e74e4f3a60 Added clean and flush to cache fsm. 2023-08-16 14:23:56 -05:00
Ross Thompson
b5ca41fd2a More progress towards cmo. 2023-08-15 18:17:15 -05:00
Ross Thompson
6284773733 The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush. 2023-08-14 16:39:18 -05:00
Ross Thompson
f678133d19 Initial CMO implementation. Just adds control signals into the L1 caches. 2023-08-14 15:43:12 -05:00
Ross Thompson
3e66653f37 Cache cleanup. 2023-07-31 14:12:53 -05:00
Ross Thompson
141e90d425
Merge pull request #372 from davidharrishmc/dev 
PLIC part select warnings fixed
 2023-07-31 11:28:28 -04:00
David Harris
55d4f28efe
Merge pull request #373 from harshinisrinath1001/main 
Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
 2023-07-30 22:46:44 -07:00
Harshini Srinath
01fc7c5284
Fixed formatting 2023-07-30 18:36:25 -07:00
Harshini Srinath
811e2fd94c
Fixed formatting 2023-07-30 18:30:23 -07:00
Harshini Srinath
01bbddc5da
Fixed formatting 2023-07-30 18:27:22 -07:00
Harshini Srinath
a697c89a2a
Fixed formatting 2023-07-30 18:18:24 -07:00
Harshini Srinath
1bc1a68210
Fixed formatting 2023-07-30 18:06:25 -07:00
Harshini Srinath
86164acc84
Fixed formatting 2023-07-30 18:00:39 -07:00
Harshini Srinath
6b5aa47f23
Fixed formatting 2023-07-30 17:54:47 -07:00
Harshini Srinath
8c7ea5a47a
Fixed formatting 2023-07-30 17:46:23 -07:00
Harshini Srinath
69711503a8
Fixed formatting 2023-07-30 17:39:37 -07:00
Harshini Srinath
70599d3153
Fixed formatting 2023-07-30 17:38:22 -07:00
Harshini Srinath
2846a2f567
Fixed spacing 2023-07-30 17:32:46 -07:00
Harshini Srinath
fffde4ef7d
Fixed spacing 2023-07-30 17:22:40 -07:00
Harshini Srinath
31c09cf3cf
Fixed spacing 2023-07-30 17:21:52 -07:00
Harshini Srinath
c49944a495
Fixed spacing 2023-07-30 17:21:22 -07:00
Harshini Srinath
84d72bc203
Fixed spacing 2023-07-30 17:18:25 -07:00
Harshini Srinath
b8570c4bef
Fixed spacing 2023-07-30 16:59:27 -07:00
Harshini Srinath
872f9ed9cc
Fixed spacing 2023-07-30 16:57:57 -07:00
David Harris
f7f4c5fa7b renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
David Harris
388d699baa Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
54d6a1afa2 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Ross Thompson
8d88ef93bc Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Ross Thompson
52dc71507f Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Ross Thompson
1b8edacd8d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
David Harris
0cfb5c7b3a Formatting cleanup 2023-07-25 05:11:38 -07:00
Ross Thompson
717833b11a Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
6099b0e763 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
0063665baf Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now. 2023-07-21 16:31:26 -05:00
Ross Thompson
37078f3d9b Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
36785848a5 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
9ba3113e9c Improved critical path. 2023-07-19 14:59:37 -05:00
Ross Thompson
936b2a8c8b Optimized critial path in ifu's spill logic. 2023-07-19 14:13:46 -05:00
Ross Thompson
0e22fe5231 Removed QEMU from configurations. 2023-07-19 10:23:55 -05:00
Ross Thompson
3bf2b35704 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
c7283f8c83 Merge branch 'main' of github.com:ross144/cvw 2023-07-17 15:52:27 -05:00
Ross Thompson
80093a0eb1 Updated the FPGA zero stage bootloader. 2023-07-17 15:52:13 -05:00
Ross Thompson
20751790f6 Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations. 2023-07-14 16:31:44 -05:00
Jacob Pease
142ec857ed Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
David Harris
45667c9f4d Clean up privilege rs1 decoding and implement svinval as sfence.vma 2023-07-13 02:41:17 -07:00
Ross Thompson
58dfc15844 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
c12bc4f435 Created separate temporary testbench for xcelium. 2023-07-11 15:07:33 -05:00
Ross Thompson
05b1cce2d1 RTL changes for Xcelium. 2023-07-11 10:51:02 -05:00
Ross Thompson
e647937b27 Fixed the privilege decoder bug which prevented the fpga linux boot. 2023-07-10 17:00:06 -05:00
Ross Thompson
47ee92d6e5
Merge pull request #359 from davidharrishmc/dev 
CSR updates
 2023-07-10 13:16:57 -04:00
David Harris
c91bbc3ca8 MENVCFG only exists if U_SUPPORTED 2023-07-09 18:25:07 -07:00
Ross Thompson
4e54e5169b Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
40b2f7ff9c Updated comments. 2023-07-06 15:24:26 -05:00
Ross Thompson
dc50ddd75e Removed unused parameter. 2023-07-06 14:57:07 -05:00
Ross Thompson
0394f3232f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
74a573cedd Removed outdated commment about endianness 2023-07-06 12:41:46 -07:00
David Harris
29e62f05a4 Removed MTINST, which is not used in a system without a hypervisor 2023-07-06 12:40:53 -07:00
Ross Thompson
18278b7f4d It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga. 2023-07-06 14:07:37 -05:00
Ross Thompson
ba9d5287d9 This is at least functionally correct, but has verilator lint issues. 2023-07-06 11:53:34 -05:00
Ross Thompson
930aed0898 closer, but the wally32/64priv tests are failing. 2023-07-05 17:47:38 -05:00
Ross Thompson
c0fdd3fbca Partially solved fpga boot. 2023-07-05 17:30:55 -05:00
David Harris
19efc4eda8 Fixed comment typo 2023-07-04 11:34:58 -07:00