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Fixed issue when with flush miss.

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This commit is contained in:
Ross Thompson 2023-08-18 16:36:13 -05:00
parent e3bb0d2820
commit 6337aab757
2 changed files with 23 additions and 1 deletions
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2
src/cache/cachefsm.sv vendored
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@ -146,7 +146,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
// com back to CPU
assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD | CurrState == STATE_CMO_DONE));
assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOp[1] | CMOp[2])) | // exclusion-tag: icache StallStates
assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | ((CMOp[1] | CMOp[2]) & CacheHit))) | // exclusion-tag: icache StallStates
(CurrState == STATE_FETCH) |
(CurrState == STATE_WRITEBACK) |
(CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.

22
tests/custom/simple/cbom.s
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@ -156,6 +156,15 @@ CBOMTest_clean_step3:
cbo.inval (a1)
la a1, Destination2+448
cbo.inval (a1)
cbo.inval (a1)
cbo.inval (a1)
cbo.inval (a1)
cbo.inval (a1)
cbo.inval (a1)
cbo.inval (a1)
cbo.inval (a1)
cbo.inval (a1)
cbo.inval (a1)
# step 4 All should be invalid
CBOMTest_clean_step4:
@ -235,6 +244,14 @@ CBOMTest_clean_step6_clean_all:
cbo.clean (a1)
la a1, Destination2+448
cbo.clean (a1)
cbo.clean (a1)
cbo.clean (a1)
cbo.clean (a1)
cbo.clean (a1)
cbo.clean (a1)
cbo.clean (a1)
cbo.clean (a1)
cbo.clean (a1)
# step 8 # invalidate all remaining
CBOMTest_clean_step7_invalidate_all:
@ -324,6 +341,11 @@ CBOMTest_flush_step5_flush_all:
cbo.flush (a1)
la a1, Destination3+448
cbo.flush (a1)
cbo.flush (a1)
cbo.flush (a1)
cbo.flush (a1)
cbo.flush (a1)
cbo.flush (a1)
# step 6
CBOMTest_flush_step6_verify: