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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
This commit is contained in:
Ross Thompson
parent
b842fdb863
commit
b9af790b81
@ -185,7 +185,9 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(P.ZICSR_SUPPORTED == 1) begin : dmmu
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logic DisableTranslation; // During HPTW walk or D$ flush disable virtual memory address translation
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logic WriteAccessM;
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assign DisableTranslation = SelHPTW | FlushDCacheM;
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assign WriteAccessM = PreLSURWM[0] | (|CMOpM);
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mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
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@ -197,7 +199,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw.
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.UpdateDA(DataUpdateDAM),
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.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
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.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
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.WriteAccessM, .ReadAccessM(PreLSURWM[1]),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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end else begin // No MMU, so no PMA/page faults and no address translation
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@ -4,7 +4,7 @@ ROOT := ..
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LIBRARY_DIRS := ${ROOT}/crt0
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LIBRARY_FILES := crt0
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MARCH :=-march=rv64imfdc
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MARCH :=-march=rv64imfdczicbom
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MABI :=-mabi=lp64d
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LINKER := ${ROOT}/linker8000-0000.x
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LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
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351
tests/custom/simple/cbom.s
Normal file
351
tests/custom/simple/cbom.s
Normal file
@ -0,0 +1,351 @@
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# Written: ross1728@gmail.com Rose Thompson 17 August 2023
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# Modified:
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# Purpose: Tests the 3 Zicbom cache instructions which all operate on cacheline
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# granularity blocks of memory. Invalidate: Clears valid and dirty bits
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# and does not write back. Clean: Writes back dirty cacheline if needed
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# and clears dirty bit. Does NOT clear valid bit. Flush: Cleans and then
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# Invalidates. These operations apply to all caches in the memory system.
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# The tests are divided into three parts one for the data cache, instruction cache
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# and checks to verify the uncached regions of memory cause exceptions.
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# -----------
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# Copyright (c) 2020. RISC-V International. All rights reserved.
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# SPDX-License-Identifier: BSD-3-Clause
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# -----------
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#
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# This assembly file tests the fence.i instruction of the RISC-V Zifencei extension.
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#
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.section .text
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.globl CBOMTest
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.type CBOMTest, @function
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CBOMTest:
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# *** TODO
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# first need to discover the length of the cacheline.
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# for now assume it is 64 bytes
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addi sp, sp, -16
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sd s0, 0(sp)
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sd ra, 8(sp)
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la s0, signature
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################################################################################
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# INVALIDATE D$
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################################################################################
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# theory of operation
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# 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
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# 2. Then verify the second region has the same data
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# 3. Invalidate the second region
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# 4. Verify the second region has the original invalid data
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# DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated
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# but the next should have the copied data.
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# step 1
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CBOMTest_inval_step1:
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la a0, SourceData
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la a1, Destination1
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li a2, 64
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jal ra, memcpy8
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# step 2
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CBOMTest_inval_step2:
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la a0, SourceData
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la a1, Destination1
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 3
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CBOMTest_inval_step3:
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la a1, Destination1
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cbo.inval (a1)
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# step 4 (should be Invalid)
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la a0, DeadBeafData1
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la a1, Destination1
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 4 next line (should still be valid)
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CBOMTest_inval_step4:
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la a0, SourceData+64
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la a1, Destination1+64
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 3 (Invalidate all remaining lines)
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CBOMTest_inval_step3_all:
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la a1, Destination1+64
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cbo.inval (a1)
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cbo.inval (a1) # verify invalidating an already non present line does not cause an issue.
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la a1, Destination1+128
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cbo.inval (a1)
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la a1, Destination1+192
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cbo.inval (a1)
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la a1, Destination1+256
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cbo.inval (a1)
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la a1, Destination1+320
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cbo.inval (a1)
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la a1, Destination1+384
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cbo.inval (a1)
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la a1, Destination1+448
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cbo.inval (a1)
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# step 4 All should be invalid
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CBOMTest_inval_step4_all:
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la a0, DeadBeafData1
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la a1, Destination1
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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################################################################################
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# Clean D$
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################################################################################
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# theory of operation
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# 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
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# 2. Then verify the second region has the same data
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# 3. Invalidate the second region
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# 4. Verify the second region has the original invalid data
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# 5. Repeat step 1
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# 6. Clean cachelines
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# 7. Verify the second region has the same data
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# 8. Invalidate the second region
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# 9. Verify again but this time it should contain the same data
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# DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated
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# but the next should have the copied data.
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# step 1
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CBOMTest_clean_step1:
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la a0, SourceData
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la a1, Destination2
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li a2, 64
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jal ra, memcpy8
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# step 2
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CBOMTest_clean_step2:
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la a0, SourceData
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la a1, Destination2
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 3
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CBOMTest_clean_step3:
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la a1, Destination2
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cbo.inval (a1)
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la a1, Destination2+64
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cbo.inval (a1)
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la a1, Destination2+128
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cbo.inval (a1)
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la a1, Destination2+192
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cbo.inval (a1)
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la a1, Destination2+256
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cbo.inval (a1)
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la a1, Destination2+320
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cbo.inval (a1)
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la a1, Destination2+384
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cbo.inval (a1)
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la a1, Destination2+448
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cbo.inval (a1)
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# step 4 All should be invalid
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CBOMTest_clean_step4:
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la a0, DeadBeafData1
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la a1, Destination2
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 5
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CBOMTest_clean_step5:
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la a0, SourceData
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la a1, Destination2
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li a2, 64
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jal ra, memcpy8
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# step 6 only clean 1 line
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CBOMTest_clean_step6:
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la a1, Destination2
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cbo.clean (a1)
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# step 7 only check that 1 line
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CBOMTest_clean_step7:
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la a0, SourceData
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la a1, Destination2
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 8 invalidate that 1 line and the next
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CBOMTest_clean_step8:
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la a1, Destination2
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cbo.inval (a1)
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la a1, Destination2+64
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cbo.inval (a1)
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# step 9 that 1 line should contain the valid data
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CBOMTest_clean_step9_line1:
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la a0, SourceData
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la a1, Destination2
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 9 the next should contain the invalid data
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CBOMTest_clean_step9_line2:
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la a0, DeadBeafData1
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la a1, Destination2+64
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li a2, 8
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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# step 5 # now recopy the one we just corrupted
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CBOMTest_clean_step5_recopy_line2:
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la a0, SourceData+64
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la a1, Destination2+64
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li a2, 8
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jal ra, memcpy8
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# step 6 # clean the remaining
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CBOMTest_clean_step6_clean_all:
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la a1, Destination2+64
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cbo.clean (a1)
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la a1, Destination2+128
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cbo.clean (a1)
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la a1, Destination2+192
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cbo.clean (a1)
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la a1, Destination2+256
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cbo.clean (a1)
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la a1, Destination2+320
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cbo.clean (a1)
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la a1, Destination2+384
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cbo.clean (a1)
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la a1, Destination2+448
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cbo.clean (a1)
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# step 8 # invalidate all remaining
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CBOMTest_clean_step7_invalidate_all:
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la a1, Destination2
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cbo.inval (a1)
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la a1, Destination2+64
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cbo.inval (a1)
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la a1, Destination2+128
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cbo.inval (a1)
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la a1, Destination2+192
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cbo.inval (a1)
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la a1, Destination2+256
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cbo.inval (a1)
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la a1, Destination2+320
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cbo.inval (a1)
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la a1, Destination2+384
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cbo.inval (a1)
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la a1, Destination2+448
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cbo.inval (a1)
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# step 9 # check all
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CBOMTest_clean_step9_check_all:
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la a0, SourceData
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la a1, Destination2
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li a2, 64
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jal ra, memcmp8
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sd a0, 0(s0) # should be -1
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addi s0, s0, 8
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ld s0, 0(sp)
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ld ra, 8(sp)
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addi sp, sp, 16
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ret
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.section .text
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.type memcpy8, @function
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memcpy8:
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# a0 is the source
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# a1 is the dst
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# a2 is the number of 8 byte words
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mv t0, a0
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mv t1, a1
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li t2, 0
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memcpy8_loop:
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ld t3, 0(t0)
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sd t3, 0(t1)
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addi t0, t0, 8
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addi t1, t1, 8
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addi t2, t2, 1
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blt t2, a2, memcpy8_loop
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ret
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.section .text
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.type memcmp8, @function
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# returns which index mismatch, -1 if none
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memcmp8:
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# a0 is the source1
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# a1 is the source2
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# a2 is the number of 8 byte words
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mv t0, a0
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mv t1, a1
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li t2, 0
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memcmp8_loop:
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ld t3, 0(t0)
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ld t4, 0(t1)
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bne t3, t4, memcmp8_ne
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addi t0, t0, 8
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addi t1, t1, 8
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addi t2, t2, 1
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blt t2, a2, memcmp8_loop
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li a0, -1
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ret
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memcmp8_ne:
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mv a0, t2
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ret
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.data
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.align 7
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DeadBeafData1:
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.fill 64, 8, 0xdeadbeefdeadbeef
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SourceData:
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.int 0, 1, 2, 3, 4, 5, 6, 7
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.int 8, 9, 10, 11, 12, 13, 14, 15
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.int 16, 17, 18, 19, 20, 21, 22, 23
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.int 24, 25, 26, 27, 28, 29, 30, 31
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.int 32, 33, 34, 35, 36, 37, 38, 39
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.int 40, 41, 42, 43, 44, 45, 46, 47
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.int 48, 49, 50, 51, 52, 53, 54, 55
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.int 56, 57, 58, 59, 60, 61, 62, 63
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.int 64, 65, 66, 67, 68, 69, 70, 71
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.int 72, 73, 74, 75, 76, 77, 79, 79
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.int 80, 81, 82, 83, 84, 85, 86, 87
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.int 88, 89, 90, 91, 92, 93, 94, 95
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.int 96, 97, 98, 99, 100, 101, 102, 103
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.int 104, 105, 106, 107, 108, 109, 110, 111
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.int 112, 113, 114, 115, 116, 117, 118, 119
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.int 120, 121, 122, 123, 124, 125, 126, 127
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Destination1:
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.fill 64, 8, 0xdeadbeefdeadbeef
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Destination2:
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.fill 64, 8, 0xdeadbeefdeadbeef
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Destination3:
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.fill 64, 8, 0xdeadbeefdeadbeef
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Destination4:
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.fill 64, 8, 0xdeadbeefdeadbeef
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signature:
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.fill 16, 8, 0x0bad0bad0bad0bad
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@ -12,4 +12,5 @@ void global_hist_3_space_test();
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void global_hist_4_space_test();
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void global_hist_6_space_test();
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void oneLoopTest();
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void CBOMTest();
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#endif
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@ -8,7 +8,8 @@ int main(){
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global_hist_3_space_test();
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global_hist_2_space_test();
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global_hist_1_space_test();
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global_hist_0_space_test();
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global_hist_0_space_test();
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CBOMTest();
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int res = 1;
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if (res < 0) {
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fail();
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