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https://github.com/openhwgroup/cvw
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Fixed formatting
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Harshini Srinath
GitHub
parent
1bc1a68210
commit
a697c89a2a
@ -28,100 +28,100 @@
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module postprocess import cvw::*; #(parameter cvw_t P) (
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// general signals
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input logic Xs, Ys, // input signs
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input logic [P.NF:0] Xm, Ym, Zm, // input mantissas
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input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic [P.FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
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input logic [2:0] OpCtrl, // choose which opperation (look below for values)
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input logic XZero, YZero, // inputs are zero
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input logic XInf, YInf, ZInf, // inputs are infinity
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input logic XNaN, YNaN, ZNaN, // inputs are NaN
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input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
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input logic [1:0] PostProcSel, // select result to be written to fp register
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input logic Xs, Ys, // input signs
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input logic [P.NF:0] Xm, Ym, Zm, // input mantissas
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input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic [P.FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
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input logic [2:0] OpCtrl, // choose which opperation (look below for values)
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input logic XZero, YZero, // inputs are zero
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input logic XInf, YInf, ZInf, // inputs are infinity
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input logic XNaN, YNaN, ZNaN, // inputs are NaN
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input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
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input logic [1:0] PostProcSel, // select result to be written to fp register
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//fma signals
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input logic FmaAs, // the modified Z sign - depends on instruction
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input logic FmaPs, // the product's sign
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input logic FmaSs, // Sum sign
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input logic [P.NE+1:0] FmaSe, // the sum's exponent
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input logic [3*P.NF+3:0] FmaSm, // the positive sum
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input logic FmaASticky, // sticky bit that is calculated during alignment
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input logic [$clog2(3*P.NF+5)-1:0] FmaSCnt, // the normalization shift count
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input logic FmaAs, // the modified Z sign - depends on instruction
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input logic FmaPs, // the product's sign
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input logic FmaSs, // Sum sign
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input logic [P.NE+1:0] FmaSe, // the sum's exponent
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input logic [3*P.NF+3:0] FmaSm, // the positive sum
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input logic FmaASticky, // sticky bit that is calculated during alignment
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input logic [$clog2(3*P.NF+5)-1:0] FmaSCnt, // the normalization shift count
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//divide signals
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input logic DivSticky, // divider sticky bit
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input logic [P.NE+1:0] DivQe, // divsqrt exponent
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input logic [P.DIVb:0] DivQm, // divsqrt significand
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input logic DivSticky, // divider sticky bit
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input logic [P.NE+1:0] DivQe, // divsqrt exponent
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input logic [P.DIVb:0] DivQm, // divsqrt significand
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// conversion signals
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input logic CvtCs, // the result's sign
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input logic [P.NE:0] CvtCe, // the calculated expoent
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input logic CvtResSubnormUf, // the convert result is subnormal or underflows
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input logic [P.LOGCVTLEN-1:0] CvtShiftAmt,// how much to shift by
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input logic ToInt, // is fp->int (since it's writting to the integer register)
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input logic [P.CVTLEN-1:0] CvtLzcIn, // input to the Leading Zero Counter (without msb)
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input logic IntZero, // is the integer input zero
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input logic CvtCs, // the result's sign
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input logic [P.NE:0] CvtCe, // the calculated expoent
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input logic CvtResSubnormUf, // the convert result is subnormal or underflows
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input logic [P.LOGCVTLEN-1:0] CvtShiftAmt, // how much to shift by
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input logic ToInt, // is fp->int (since it's writting to the integer register)
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input logic [P.CVTLEN-1:0] CvtLzcIn, // input to the Leading Zero Counter (without msb)
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input logic IntZero, // is the integer input zero
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// final results
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output logic [P.FLEN-1:0] PostProcRes,// postprocessor final result
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output logic [4:0] PostProcFlg,// postprocesser flags
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output logic [P.XLEN-1:0] FCvtIntRes // the integer conversion result
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output logic [P.FLEN-1:0] PostProcRes, // postprocessor final result
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output logic [4:0] PostProcFlg, // postprocesser flags
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output logic [P.XLEN-1:0] FCvtIntRes // the integer conversion result
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);
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// general signals
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logic Rs; // result sign
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logic [P.NF-1:0] Rf; // Result fraction
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logic [P.NE-1:0] Re; // Result exponent
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logic Ms; // norMalized sign
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logic [P.CORRSHIFTSZ-1:0] Mf; // norMalized fraction
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logic [P.NE+1:0] Me; // normalized exponent
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logic [P.NE+1:0] FullRe; // Re with bits to determine sign and overflow
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logic UfPlus1; // do you add one (for determining underflow flag)
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logic [P.LOGNORMSHIFTSZ-1:0] ShiftAmt; // normalization shift amount
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logic [P.NORMSHIFTSZ-1:0] ShiftIn; // input to normalization shift
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logic [P.NORMSHIFTSZ-1:0] Shifted; // the ouput of the normalized shifter (before shift correction)
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logic Plus1; // add one to the final result?
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logic Overflow; // overflow flag used to select results
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logic Invalid; // invalid flag used to select results
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logic Guard, Round, Sticky; // bits needed to determine rounding
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logic [P.FMTBITS-1:0] OutFmt; // output format
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logic Rs; // result sign
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logic [P.NF-1:0] Rf; // Result fraction
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logic [P.NE-1:0] Re; // Result exponent
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logic Ms; // norMalized sign
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logic [P.CORRSHIFTSZ-1:0] Mf; // norMalized fraction
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logic [P.NE+1:0] Me; // normalized exponent
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logic [P.NE+1:0] FullRe; // Re with bits to determine sign and overflow
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logic UfPlus1; // do you add one (for determining underflow flag)
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logic [P.LOGNORMSHIFTSZ-1:0] ShiftAmt; // normalization shift amount
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logic [P.NORMSHIFTSZ-1:0] ShiftIn; // input to normalization shift
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logic [P.NORMSHIFTSZ-1:0] Shifted; // the ouput of the normalized shifter (before shift correction)
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logic Plus1; // add one to the final result?
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logic Overflow; // overflow flag used to select results
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logic Invalid; // invalid flag used to select results
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logic Guard, Round, Sticky; // bits needed to determine rounding
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logic [P.FMTBITS-1:0] OutFmt; // output format
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// fma signals
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logic [P.NE+1:0] FmaMe; // exponent of the normalized sum
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logic FmaSZero; // is the sum zero
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logic [3*P.NF+5:0] FmaShiftIn; // fma shift input
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logic [P.NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results
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logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection
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logic [$clog2(3*P.NF+5)-1:0] FmaShiftAmt;// normalization shift amount for fma
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logic [P.NE+1:0] FmaMe; // exponent of the normalized sum
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logic FmaSZero; // is the sum zero
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logic [3*P.NF+5:0] FmaShiftIn; // fma shift input
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logic [P.NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results
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logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection
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logic [$clog2(3*P.NF+5)-1:0] FmaShiftAmt; // normalization shift amount for fma
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// division singals
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logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount
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logic [P.NORMSHIFTSZ-1:0] DivShiftIn; // divsqrt shift input
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logic [P.NE+1:0] Qe; // divsqrt corrected exponent after corretion shift
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logic DivByZero; // divide by zero flag
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logic DivResSubnorm; // is the divsqrt result subnormal
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logic DivSubnormShiftPos; // is the divsqrt subnorm shift amout positive (not underflowed)
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logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount
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logic [P.NORMSHIFTSZ-1:0] DivShiftIn; // divsqrt shift input
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logic [P.NE+1:0] Qe; // divsqrt corrected exponent after corretion shift
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logic DivByZero; // divide by zero flag
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logic DivResSubnorm; // is the divsqrt result subnormal
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logic DivSubnormShiftPos; // is the divsqrt subnorm shift amout positive (not underflowed)
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// conversion signals
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logic [P.CVTLEN+P.NF:0] CvtShiftIn; // number to be shifted for converter
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logic [1:0] CvtNegResMsbs; // most significant bits of possibly negated int result
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logic [P.XLEN+1:0] CvtNegRes; // possibly negated integer result
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logic CvtResUf; // did the convert result underflow
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logic IntInvalid; // invalid integer flag
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logic [P.CVTLEN+P.NF:0] CvtShiftIn; // number to be shifted for converter
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logic [1:0] CvtNegResMsbs; // most significant bits of possibly negated int result
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logic [P.XLEN+1:0] CvtNegRes; // possibly negated integer result
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logic CvtResUf; // did the convert result underflow
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logic IntInvalid; // invalid integer flag
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// readability signals
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logic Mult; // multiply opperation
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logic Sqrt; // is the divsqrt opperation sqrt
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logic Int64; // is the integer 64 bits?
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logic Signed; // is the opperation with a signed integer?
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logic IntToFp; // is the opperation an int->fp conversion?
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logic CvtOp; // convertion opperation
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logic FmaOp; // fma opperation
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logic DivOp; // divider opperation
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logic InfIn; // are any of the inputs infinity
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logic NaNIn; // are any of the inputs NaN
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logic Mult; // multiply opperation
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logic Sqrt; // is the divsqrt opperation sqrt
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logic Int64; // is the integer 64 bits?
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logic Signed; // is the opperation with a signed integer?
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logic IntToFp; // is the opperation an int->fp conversion?
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logic CvtOp; // convertion opperation
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logic FmaOp; // fma opperation
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logic DivOp; // divider opperation
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logic InfIn; // are any of the inputs infinity
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logic NaNIn; // are any of the inputs NaN
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// signals to help readability
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assign Signed = OpCtrl[0];
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assign Int64 = OpCtrl[1];
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assign Signed = OpCtrl[0];
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assign Int64 = OpCtrl[1];
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assign IntToFp = OpCtrl[2];
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assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
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assign CvtOp = (PostProcSel == 2'b00);
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assign FmaOp = (PostProcSel == 2'b10);
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assign DivOp = (PostProcSel == 2'b01);
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assign Sqrt = OpCtrl[0];
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assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
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assign CvtOp = (PostProcSel == 2'b00);
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assign FmaOp = (PostProcSel == 2'b10);
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assign DivOp = (PostProcSel == 2'b01);
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assign Sqrt = OpCtrl[0];
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// is there an input of infinity or NaN being used
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assign InfIn = XInf|YInf|ZInf;
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@ -153,19 +153,19 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
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case(PostProcSel)
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2'b10: begin // fma
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ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(3*P.NF+5){1'b0}}, FmaShiftAmt};
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ShiftIn = {FmaShiftIn, {P.NORMSHIFTSZ-(3*P.NF+6){1'b0}}};
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ShiftIn = {FmaShiftIn, {P.NORMSHIFTSZ-(3*P.NF+6){1'b0}}};
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end
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2'b00: begin // cvt
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ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt};
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ShiftIn = {CvtShiftIn, {P.NORMSHIFTSZ-P.CVTLEN-P.NF-1{1'b0}}};
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ShiftIn = {CvtShiftIn, {P.NORMSHIFTSZ-P.CVTLEN-P.NF-1{1'b0}}};
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end
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2'b01: begin //divsqrt
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ShiftAmt = DivShiftAmt;
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ShiftIn = DivShiftIn;
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ShiftIn = DivShiftIn;
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end
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default: begin
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ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}};
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ShiftIn = {P.NORMSHIFTSZ{1'bx}};
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ShiftIn = {P.NORMSHIFTSZ{1'bx}};
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end
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endcase
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