Ross Thompson
16b3c64234
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-16 14:59:03 -05:00
Ross Thompson
b9a19304db
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
David Harris
68d9c99fba
Added WFI support to IFU to keep it in the pipeline
2022-04-14 17:26:17 +00:00
David Harris
a28831b83e
Added WFI to the testbench instruction name decoder
2022-04-14 17:12:11 +00:00
David Harris
855d68afde
WFI should set EPC to PC+4
2022-04-14 17:05:22 +00:00
bbracker
fe53dd1683
fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
2022-04-14 09:23:21 -07:00
bbracker
eb21e34000
fix ReadDataM forcing
2022-04-13 15:32:00 -07:00
Ross Thompson
2e8afd071e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-13 13:39:47 -05:00
bbracker
5de92af0b1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-13 05:35:56 -07:00
bbracker
735c75af55
change interrupt spoofing to happen at negative clock edges
2022-04-13 04:31:23 -07:00
bbracker
52ed99ca1b
improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
2022-04-13 03:37:53 -07:00
bbracker
03f1c01f14
whoops forgot to update AttemptedInstructionCount in interrupt spoofing
2022-04-13 00:49:37 -07:00
bbracker
d3e9703c19
change testbench-linux to by default use attempted instruction count for warning/error messages
2022-04-12 21:22:08 -07:00
Ross Thompson
bb6f1cf816
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-12 19:38:04 -05:00
Ross Thompson
fc173a7954
Missed the force on uart for no tracking.
2022-04-12 19:37:44 -05:00
Ross Thompson
ff826fdb02
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-12 17:56:48 -05:00
Ross Thompson
7d0462dc59
UART and clock speed changes to support 30Mhz.
2022-04-12 17:56:36 -05:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
02d6829f8e
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
f995ec2a54
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-10 13:41:27 -05:00
Ross Thompson
c3d9eafe60
Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
2022-04-10 13:27:54 -05:00
bbracker
aa71fe542d
upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs
2022-04-08 13:45:27 -07:00
bbracker
3b6cb5f0ba
small signs of life on new interrupt spoofing
2022-04-08 12:32:30 -07:00
Ross Thompson
2294cbc1c6
Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
2022-04-07 16:56:28 -05:00
Ross Thompson
5e4682fb65
Fixed typo in tests.vh
2022-04-07 16:28:28 -05:00
Katherine Parry
c307cff503
fixed errors and warnings in rv32e
2022-04-07 17:21:20 +00:00
Kip Macsai-Goren
7425c49f58
updated test signature locations
2022-04-06 07:28:38 +00:00
Kip Macsai-Goren
c82667653c
Added missing ZFH macro to new configs
2022-04-06 07:13:51 +00:00
David Harris
c4f5b3fd7c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-04-05 23:23:47 +00:00
David Harris
c22d6f2848
Added bootmem source ccode
2022-04-05 23:22:53 +00:00
Ross Thompson
9517fe9faf
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-05 15:42:07 -05:00
Ross Thompson
7abde2b566
Increazed fpga clock speed to 35Mhz.
...
linux boot is much faster.
2022-04-05 15:09:49 -05:00
Katherine Parry
20885f4dea
generating all testfloat vectors
2022-04-04 17:17:12 +00:00
Ross Thompson
0ed34b8e63
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-04 10:56:10 -05:00
Ross Thompson
64846c800e
Constraint changes for 40Mhz wally.
2022-04-04 10:50:48 -05:00
Ross Thompson
0806d1a134
Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.
2022-04-04 10:38:37 -05:00
Ross Thompson
d83db2cde5
Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
2022-04-04 09:57:26 -05:00
Ross Thompson
fd9a33e453
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-03 17:56:55 -05:00
Ross Thompson
e7abcd862f
fpga simulation works again.
2022-04-03 17:31:07 -05:00
David Harris
6966554ee8
Fixed bug with CSRRS/CSRRC for MIP/SIP
2022-04-03 20:18:25 +00:00
Ross Thompson
d135866098
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-02 16:39:54 -05:00
Ross Thompson
5ef6cde52e
Added more ILA signals.
2022-04-02 16:39:45 -05:00
Kip Macsai-Goren
cdea062287
added RV64IA config to have a config without compressed instructions
2022-04-02 18:24:08 +00:00
Ross Thompson
987236e463
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-01 17:18:25 -05:00
Ross Thompson
57eba4355e
Updated the fpga test bench.
2022-04-01 17:14:47 -05:00
Ross Thompson
f58a1eff9e
Fixed linting issues.
2022-04-01 15:20:45 -05:00
Ross Thompson
178ecaa451
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-01 12:50:34 -05:00
Ross Thompson
0340c0fd44
Added wave config
...
added new signals to ILA.
2022-04-01 12:44:14 -05:00
bbracker
cbff9a7755
expand WALLY-PERIPH test to use SEIP on PLIC context 1
2022-03-31 18:02:06 -07:00
bbracker
36c30b14c1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-31 17:54:43 -07:00
