David Harris
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bcb52acfba
|
bram synthesis test
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2022-08-23 19:34:45 -07:00 |
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Ross Thompson
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e4cbb43c67
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 18:52:15 -05:00 |
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Ross Thompson
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642dc170d7
|
Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.
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2022-08-23 18:51:11 -05:00 |
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David Harris
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5eebd521c5
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Fixed FPU-IEU forwarding stall
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2022-08-23 14:14:41 -07:00 |
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David Harris
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d72068d582
|
Only stall FPU to IEU on convert instructions with dependencies
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2022-08-23 12:57:18 -07:00 |
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David Harris
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05aa18fe14
|
Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
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2022-08-23 12:17:19 -07:00 |
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David Harris
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d19fc99bf0
|
Simplify IEU-FP datapath
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2022-08-23 11:16:36 -07:00 |
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David Harris
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f72d07adce
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Improved illegal instruction checking in FPU
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2022-08-23 11:08:02 -07:00 |
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David Harris
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c61dba6192
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Fixed LSU typos
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2022-08-23 10:23:08 -07:00 |
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David Harris
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2a1bd53663
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 10:14:59 -07:00 |
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David Harris
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029aecabf7
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typo in srtfsm
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2022-08-23 10:14:54 -07:00 |
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Katherine Parry
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fe0c6afe58
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-23 16:36:32 +00:00 |
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Katherine Parry
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4e33ead413
|
renamed rounding bits to L,G,R,S and fixed lint warning
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2022-08-23 16:36:20 +00:00 |
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Ross Thompson
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20ba6fd19c
|
Reversed order of supported sized in adrdecs.
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2022-08-23 11:14:53 -05:00 |
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Ross Thompson
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5efec3b1f3
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Replaced FPU data replicaiton on WriteData bus with 0 extention.
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2022-08-23 10:46:03 -05:00 |
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Ross Thompson
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aa5cbab0d8
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Replaced LSU data replication with 0 extention.
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2022-08-23 10:43:47 -05:00 |
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Ross Thompson
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3b07584403
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Updated the names of the *WriteDataM inside the LSU to more meaningful names.
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
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2022-08-23 10:34:39 -05:00 |
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David Harris
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e714b75888
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
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David Harris
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3c91df95d9
|
Named HTRANS states in busfsm
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2022-08-22 13:56:46 -07:00 |
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David Harris
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6cfbf95d98
|
Renamed signals for LSU - FPU interface
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2022-08-22 13:47:56 -07:00 |
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David Harris
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c789b5789c
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renamed GrantData to LSUGrant
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2022-08-22 13:47:19 -07:00 |
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David Harris
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0e489443f2
|
Finished FPU-LSU interface cleanup
|
2022-08-22 13:43:04 -07:00 |
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David Harris
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ea153e0aad
|
Removed FStore2 and simplified HPTW
|
2022-08-22 13:29:54 -07:00 |
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David Harris
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8444eca57c
|
Simplified FPU-LSU interface to skip IEU
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2022-08-22 13:29:20 -07:00 |
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David Harris
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774cddf33c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-22 13:28:54 -07:00 |
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David Harris
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d556adde16
|
Simplified FPU-LSU interface to skip IEU
|
2022-08-22 13:28:51 -07:00 |
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Katherine Parry
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a9be193a35
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-22 17:16:25 +00:00 |
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Katherine Parry
|
36be692c0b
|
sqrt passes - lint warnings remain
|
2022-08-22 17:16:12 +00:00 |
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David Harris
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2e20b3ed72
|
Removed 2-cycle FPU-IEU latency stall
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2022-08-22 16:14:15 +00:00 |
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David Harris
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bdfc49f847
|
moved CSA to generic
|
2022-08-22 08:41:23 +00:00 |
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David Harris
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f10793e85d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-22 08:28:31 +00:00 |
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David Harris
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f6f09db4fb
|
Commented out unused comparators
|
2022-08-22 08:28:28 +00:00 |
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Ross Thompson
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dbbb3ff1d1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-21 16:03:11 -05:00 |
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Ross Thompson
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ebe4339953
|
Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
|
2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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85dbec5969
|
Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
|
2022-08-21 15:28:29 -05:00 |
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Ross Thompson
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f3f0f12904
|
Removed logic from Verilog wrapper.
|
2022-08-21 14:07:43 -05:00 |
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Katherine Parry
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a191603a1a
|
fixed -1 issue in division
|
2022-08-20 00:53:45 +00:00 |
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Ross Thompson
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2ba390adf4
|
Possible reduction of ignorerequest.
|
2022-08-19 18:07:44 -05:00 |
|
Ross Thompson
|
517c0f6c35
|
Changed signal names.
|
2022-08-17 16:12:04 -05:00 |
|
Ross Thompson
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f6e5746e59
|
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
|
2022-08-17 16:09:20 -05:00 |
|
Ross Thompson
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299aefb76a
|
Removed old code from interlockfsm.
|
2022-08-17 12:52:56 -05:00 |
|
Katherine Parry
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9549c23f45
|
sqrt tests in regression uncommented and pass
|
2022-08-07 23:38:10 +00:00 |
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Katherine Parry
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cb0c1b7488
|
radix-2 1 copy passes testfloat
|
2022-08-06 22:54:05 +00:00 |
|
Katherine Parry
|
de6ae471bc
|
fixed fsw problem and removed 2 bit shift from shift correction
|
2022-08-03 22:16:51 +00:00 |
|
David Harris
|
e70b28f7f6
|
FMA cleanup
|
2022-08-02 07:42:32 -07:00 |
|
David Harris
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2b932c4b80
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-02 07:34:12 -07:00 |
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David Harris
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887e4c73fb
|
Moved InvA to sign block; simplified fmaexpadd coding
|
2022-08-02 07:34:09 -07:00 |
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Ross Thompson
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413a9bf58b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-01 22:09:11 -05:00 |
|
Ross Thompson
|
57fcf0ef79
|
Fixed fstore2 in cache?
|
2022-08-01 22:04:44 -05:00 |
|
David Harris
|
06c4f18cd1
|
merged lza back into main
|
2022-08-01 19:45:21 -07:00 |
|
David Harris
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8147f75399
|
Fixed fmaadd to work with new LZA
|
2022-08-01 19:40:55 -07:00 |
|
Ross Thompson
|
797d9e3610
|
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
|
2022-08-01 21:12:25 -05:00 |
|
Ross Thompson
|
3cd8404917
|
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
|
2022-08-01 21:08:14 -05:00 |
|
Ross Thompson
|
3612db2d70
|
pulled swbbytemask out of subword write.
|
2022-08-01 20:48:45 -05:00 |
|
David Harris
|
7e4b04ff64
|
Parameterized fmalza
|
2022-08-01 16:18:02 -07:00 |
|
David Harris
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94fa7a00e7
|
Completed LZA simplificaiton
|
2022-08-01 16:13:16 -07:00 |
|
David Harris
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3b937b73fd
|
lza cleanup
|
2022-08-01 16:01:02 -07:00 |
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David Harris
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b614f165fb
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-01 15:47:58 -07:00 |
|
David Harris
|
91597bba87
|
lza cleanup
|
2022-08-01 15:47:03 -07:00 |
|
David Harris
|
f56b26ec40
|
lza cleanup
|
2022-08-01 15:43:48 -07:00 |
|
David Harris
|
c3e9719c99
|
lza cleanup
|
2022-08-01 15:40:12 -07:00 |
|
David Harris
|
d6b5e7a6ef
|
lza cleanup
|
2022-08-01 15:37:09 -07:00 |
|
Katherine Parry
|
8ff3a693af
|
regression passes fpu tests
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2022-08-01 19:56:25 +00:00 |
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Katherine Parry
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9c68f85822
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-01 19:55:50 +00:00 |
|
David Harris
|
2869d67e50
|
more lza cleanup
|
2022-08-01 12:34:00 -07:00 |
|
David Harris
|
b34d2065c3
|
LZA cleanup
|
2022-08-01 12:30:42 -07:00 |
|
David Harris
|
99462049e7
|
LZA refactoring switched to Pp1, Gm1, Km1
|
2022-08-01 12:20:23 -07:00 |
|
David Harris
|
3c08aabcd3
|
LZA refactoring
|
2022-08-01 11:36:21 -07:00 |
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Katherine Parry
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eddf6e9ee1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-01 18:35:07 +00:00 |
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David Harris
|
7f9b601467
|
fmalza edits to match textbook
|
2022-08-01 18:23:39 +00:00 |
|
David Harris
|
257107f908
|
Partitioned fma into separate files
|
2022-08-01 18:07:38 +00:00 |
|
Ross Thompson
|
1ee613ae6c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-31 12:48:51 -05:00 |
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Katherine Parry
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1bd6351e1f
|
re-added FStore2 in Cache
|
2022-07-29 22:54:49 +00:00 |
|
David Harris
|
93d7d7179e
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
Ross Thompson
|
40e7cda84a
|
Don't use this commit yet. Untested.
|
2022-07-24 15:40:52 -05:00 |
|
Ross Thompson
|
719b00e338
|
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
|
2022-07-24 01:20:29 -05:00 |
|
Ross Thompson
|
69d520a7eb
|
Removed replay from the config files.
|
2022-07-24 00:34:11 -05:00 |
|
Ross Thompson
|
cd68896637
|
Merged evict dirty clear with flush write back.
|
2022-07-24 00:22:43 -05:00 |
|
Ross Thompson
|
8193946996
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-23 08:41:59 -05:00 |
|
Ross Thompson
|
05484c4c05
|
signal name cleanup.
|
2022-07-22 23:36:27 -05:00 |
|
Ross Thompson
|
27e32980ad
|
cache cleanup after removing replay on cpubusy.
|
2022-07-22 23:30:25 -05:00 |
|
Ross Thompson
|
17ae1a1b1b
|
cache fsm cleanup after removal of replay.
|
2022-07-22 23:25:09 -05:00 |
|
Ross Thompson
|
abc79c6c8e
|
Possible improvement to cache which removes the cpu_busy states.
|
2022-07-22 23:20:37 -05:00 |
|
Katherine Parry
|
655e2d3810
|
merged radix-2 sqrt into divider - doesnt work yet
|
2022-07-23 00:41:18 +00:00 |
|
slmnemo
|
bfced6bfe8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 17:13:38 -07:00 |
|
slmnemo
|
ca4511b6dc
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
|
Katherine Parry
|
b3d932cd61
|
divider sizes reworked to match book
|
2022-07-22 22:02:04 +00:00 |
|
David Harris
|
d22587090b
|
Reset MSR on read
|
2022-07-22 04:29:27 +00:00 |
|
slmnemo
|
3d2c6683d8
|
Fixed UART bug related to parity and MSR/LSR
|
2022-07-21 20:35:46 -07:00 |
|
Katherine Parry
|
fbe8bb2298
|
radix-4 division integrated into srt - not tested
|
2022-07-21 19:38:06 +00:00 |
|
Katherine Parry
|
7950a675ea
|
added input enables and improved forwarding
|
2022-07-21 01:20:06 +00:00 |
|
Katherine Parry
|
a30d9c6bd8
|
turn off 2 word store durring non-fp instructions
|
2022-07-20 21:57:23 +00:00 |
|
Ross Thompson
|
1cad05fef9
|
Minor cleanup of cache.
|
2022-07-19 23:04:23 -05:00 |
|
Ross Thompson
|
8698799077
|
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
|
2022-07-19 22:42:25 -05:00 |
|
Katherine Parry
|
b26297e874
|
moved ctrl signal registers into fctrl, also a lot of code cleaning
|
2022-07-20 02:27:39 +00:00 |
|
cturek
|
0f94177765
|
small changes
|
2022-07-20 01:36:25 +00:00 |
|
Katherine Parry
|
d61f84e751
|
oprimized zeros and replaced complex ?: with always_comb
|
2022-07-19 23:44:37 +00:00 |
|
Ross Thompson
|
a79e5e11f6
|
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
|
2022-07-18 23:37:18 -05:00 |
|
Katherine Parry
|
514674417e
|
moved Se into execute stage
|
2022-07-19 01:10:10 +00:00 |
|
Katherine Parry
|
64b3e4117b
|
reworked fmashiftcalc to match book
|
2022-07-19 00:04:24 +00:00 |
|