David Harris
|
e713ba8d3e
|
MENVCFG only exists if U_SUPPORTED
|
2023-07-09 18:25:07 -07:00 |
|
David Harris
|
369e8fb5ec
|
Removed outdated commment about endianness
|
2023-07-06 12:41:46 -07:00 |
|
David Harris
|
869a7cb827
|
Removed MTINST, which is not used in a system without a hypervisor
|
2023-07-06 12:40:53 -07:00 |
|
David Harris
|
c48283801a
|
Fixed csr typos
|
2023-07-02 02:01:40 -07:00 |
|
David Harris
|
61208e486c
|
Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode
|
2023-07-02 02:00:27 -07:00 |
|
David Harris
|
b6ae5661b4
|
Added environment configuration control (menvcfg/senvcfg) of cbo instructions
|
2023-07-02 01:52:25 -07:00 |
|
David Harris
|
15314a9c9a
|
Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
|
2023-07-02 00:34:30 -07:00 |
|
Harshini Srinath
|
3593762cfa
|
Merge branch 'main' into main
|
2023-06-14 11:52:45 -07:00 |
|
Harshini Srinath
|
3f8cd8932c
|
Update csrs.sv
Program clean up
|
2023-06-13 22:16:43 -07:00 |
|
Harshini Srinath
|
12af05da02
|
Update csrm.sv
Program clean up
|
2023-06-13 22:08:06 -07:00 |
|
Harshini Srinath
|
a213f7d5a4
|
Update csrc.sv
Program clean up
|
2023-06-13 21:54:47 -07:00 |
|
Harshini Srinath
|
6aba0187d7
|
Update csr.sv
Program clean up
|
2023-06-13 21:12:49 -07:00 |
|
Harshini Srinath
|
2c6322647f
|
Update trap.sv
Program clean up
|
2023-06-12 20:31:44 -07:00 |
|
Harshini Srinath
|
dba1a77e5f
|
Update privmode.sv
Program clean up
|
2023-06-12 20:27:48 -07:00 |
|
Harshini Srinath
|
63a7649179
|
Update privileged.sv
Program clean up
|
2023-06-12 20:26:07 -07:00 |
|
Harshini Srinath
|
d2a41a6422
|
Update csru.sv
Program clean up
|
2023-06-12 20:21:55 -07:00 |
|
Harshini Srinath
|
6866a9c541
|
Update csrsr.sv
Program clean up
|
2023-06-12 20:19:47 -07:00 |
|
Harshini Srinath
|
fbdf76629f
|
Update csrsr.sv
Program clean up
|
2023-06-12 20:15:29 -07:00 |
|
Harshini Srinath
|
120cde2aea
|
Update csrs.sv
Program clean up
|
2023-06-12 19:53:41 -07:00 |
|
Harshini Srinath
|
6305412d57
|
Update csrm.sv
Program clean up
|
2023-06-12 19:42:45 -07:00 |
|
Harshini Srinath
|
61d50a18da
|
Update csri.sv
Program clean up
|
2023-06-12 19:32:04 -07:00 |
|
Harshini Srinath
|
02a11278fc
|
Update csrc.sv
Program clean up
|
2023-06-12 19:03:34 -07:00 |
|
Harshini Srinath
|
a2645dd576
|
Update csr.sv
Program clean up
|
2023-06-12 18:51:37 -07:00 |
|
David Harris
|
b70b0c7c5e
|
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
|
2023-06-09 14:40:01 -07:00 |
|
David Harris
|
df96900aa1
|
Added named support for Zicntr and Zihpm
|
2023-06-09 09:35:51 -07:00 |
|
Ross Thompson
|
918464c236
|
Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.
|
2023-06-05 15:42:05 -05:00 |
|
Ross Thompson
|
a963f0af3a
|
Updated source code to be compatible with verilator 5.011 for lint only.
|
2023-05-31 10:44:23 -05:00 |
|
Ross Thompson
|
c7e515634d
|
I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.
|
2023-05-26 13:56:51 -05:00 |
|
Ross Thompson
|
8cf38b28aa
|
The privileged unit is parameterized using Lim's method.
|
2023-05-26 12:03:46 -05:00 |
|
Ross Thompson
|
625d365f3e
|
Fixes load and store stall counters.
|
2023-05-22 10:08:49 -05:00 |
|
David Harris
|
ca61cff33f
|
CSR code cleanup
|
2023-04-27 14:12:57 -07:00 |
|
David Harris
|
6a5895e09f
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-04-27 07:30:07 -07:00 |
|
Alexa Wright
|
6ee8a9c0bd
|
Added better comment for the exclusion in privdec.sv
|
2023-04-26 16:25:55 -07:00 |
|
Alexa Wright
|
59d913949f
|
Excluded and added coverage for WFI test case.
|
2023-04-25 17:06:57 -07:00 |
|
David Harris
|
a5087818ba
|
Commented about Sstvecd trap vector alignment
|
2023-04-24 12:20:33 -07:00 |
|
Diego Herrera Vicioso
|
d29dc30288
|
Excluded coverage for impossible cases in wficountreg and status.MPRV
|
2023-04-24 02:06:53 -07:00 |
|
David Harris
|
52f49ed24d
|
Fault on writes to odd-numbered PMPCFG in RV64
|
2023-04-22 15:32:39 -07:00 |
|
Diego Herrera Vicioso
|
16fd17be39
|
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
|
2023-04-15 23:13:39 -07:00 |
|
Limnanthes Serafini
|
034c289a36
|
Misc typo and indent fixing.
|
2023-04-13 16:54:15 -07:00 |
|
Alexa Wright
|
fb517163f5
|
Excluded coverage for misaligned instructions
|
2023-04-10 23:18:25 -07:00 |
|
David Harris
|
9394389fec
|
Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed
|
2023-04-07 20:43:28 -07:00 |
|
Ross Thompson
|
da9cf02ba0
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-04-05 14:55:12 -05:00 |
|
Ross Thompson
|
394f2d65f2
|
Progress on bug 203.
|
2023-04-05 13:20:04 -05:00 |
|
David Harris
|
4552f9cf8c
|
Fixed WFI to commit when an interrupt occurs
|
2023-04-04 09:32:26 -07:00 |
|
David Harris
|
fd0c9e973d
|
Coverage improvements in ieu, hazard units
|
2023-03-31 08:33:46 -07:00 |
|
David Harris
|
da53f240d3
|
Refactored InstrValidNotFlushed into CSR Write signals
|
2023-03-30 17:06:09 -07:00 |
|
David Harris
|
406bb22b6a
|
Started factoring out InstrValidNotFlushed from CSRs
|
2023-03-30 14:56:19 -07:00 |
|
Kip Macsai-Goren
|
3805cf993a
|
unnecessary comments cleanup
|
2023-03-29 19:32:57 -07:00 |
|
Kip Macsai-Goren
|
491ef14b71
|
Resolved ImperasDV receiving incorrect cause values
|
2023-03-29 15:04:56 -07:00 |
|
David Harris
|
9d8f9e4428
|
Reduced number of bits in mcause and medeleg registers
|
2023-03-29 07:02:09 -07:00 |
|
David Harris
|
2e238c15aa
|
CSRS privileged coverage test
|
2023-03-28 04:37:56 -07:00 |
|
David Harris
|
9b7e5cec1f
|
Removed unnecessary monitor
|
2023-03-27 09:52:38 -07:00 |
|
Lee Moore
|
4bb7dadc00
|
Merge branch 'openhwgroup:main' into add-linux
|
2023-03-27 09:44:13 +01:00 |
|
Ross Thompson
|
46b1bca4fc
|
Fixed all tap/space issue in RTL.
|
2023-03-24 17:32:25 -05:00 |
|
David Harris
|
121d1cea62
|
Added csrwrites.S test case for privileged tests
|
2023-03-23 10:55:32 -07:00 |
|
eroom1966
|
259fbc8d77
|
support linux
|
2023-03-22 17:10:32 +00:00 |
|
David Harris
|
e03a533775
|
Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault
|
2023-03-22 06:29:30 -07:00 |
|
David Harris
|
80fc851332
|
Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0
|
2023-03-22 04:41:57 -07:00 |
|
David Harris
|
a1eccf37dc
|
Fix Issue 145
|
2023-03-22 04:33:14 -07:00 |
|
David Harris
|
4cde207958
|
Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression.
|
2023-03-18 10:10:58 -07:00 |
|
David Harris
|
6922298f21
|
Replaced FenceM with InvalidateICacheM for event counting of fence.i
|
2023-03-18 09:24:31 -07:00 |
|
Ross Thompson
|
68b437ce92
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-03-09 13:29:38 -06:00 |
|
Ross Thompson
|
4db17cde2f
|
Updated testbench to record coremark performance counters.
Added comment about mtval probably not being correct for compressed instructions.
|
2023-03-08 17:11:27 -06:00 |
|
Kip Macsai-Goren
|
a38f7cc8a1
|
added reset values to stime and stimecmp registers
|
2023-03-04 15:06:15 -08:00 |
|
Ross Thompson
|
0cb5369351
|
Renamed BTB misprediction to BTA.
|
2023-03-03 00:18:34 -06:00 |
|
Ross Thompson
|
5b5677ccb8
|
Added divide cycle counter.
|
2023-03-02 23:59:52 -06:00 |
|
Ross Thompson
|
aabb454d1c
|
Added the i and d cache cycle counters.
|
2023-03-02 23:54:56 -06:00 |
|
Ross Thompson
|
cfca77172e
|
Added fence counter.
|
2023-03-02 23:29:20 -06:00 |
|
Ross Thompson
|
f32f8c109a
|
Added csr write counter, sfence vma counter, interrupt counter, and exception counter.
|
2023-03-02 23:21:29 -06:00 |
|
Ross Thompson
|
a313b10912
|
Added store stall to performance counters.
|
2023-03-02 23:10:54 -06:00 |
|
Ross Thompson
|
2dd693a3b3
|
Reordered performance counters and added space for new ones.
|
2023-03-02 23:04:31 -06:00 |
|
Ross Thompson
|
b98e007a53
|
Cleaned up branch predictor performance counters.
|
2023-03-01 17:05:42 -06:00 |
|
Ross Thompson
|
a6917d07f3
|
Name cleanup.
|
2023-02-28 17:48:58 -06:00 |
|
Ross Thompson
|
2ebe600f54
|
Name changes to reflect diagrams.
|
2023-02-28 15:37:25 -06:00 |
|
Ross Thompson
|
72be4318b8
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
|
2023-02-26 12:06:06 -06:00 |
|
David Harris
|
fe161f6bde
|
Fixed missing assign when SSTC is not supported
|
2023-02-26 07:12:13 -08:00 |
|
David Harris
|
8895114152
|
Fixed SSTC being unusable in M-MODE without Status.TM. Disable STIMECMP registers when SSTC_SUPPORTED = 0
|
2023-02-26 06:30:43 -08:00 |
|
Ross Thompson
|
8bd4a4c35b
|
Renamed signals to match new figures.
|
2023-02-24 19:51:47 -06:00 |
|
David Harris
|
f0566173e6
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-02-21 09:58:18 -08:00 |
|
David Harris
|
a445e53e8d
|
Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.
|
2023-02-21 09:32:17 -08:00 |
|
Ross Thompson
|
fdd007a903
|
Found a bug where the d and i cache misses were not recorded in the performance counters.
|
2023-02-20 16:00:29 -06:00 |
|
David Harris
|
5b370bdc0f
|
Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.
|
2023-02-16 07:37:12 -08:00 |
|
David Harris
|
755c795f91
|
Moved STATUS_FS_INT write to if statement to properly prioritize
|
2023-02-07 06:55:42 -08:00 |
|
David Harris
|
e92605e2de
|
Disabled STATUS_FS at reset, fixing issue #71
|
2023-02-07 06:31:14 -08:00 |
|
David Harris
|
97ee3732fe
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-02-03 08:36:11 -08:00 |
|
David Harris
|
78eb90715c
|
Removed pipelined level of hierarchy
|
2023-02-02 14:14:11 -08:00 |
|