David Harris 80fc851332 Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0		2023-03-22 04:41:57 -07:00
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csr.sv	Fix Issue 145	2023-03-22 04:33:14 -07:00
csrc.sv	Replaced FenceM with InvalidateICacheM for event counting of fence.i	2023-03-18 09:24:31 -07:00
csri.sv	Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression.	2023-03-18 10:10:58 -07:00
csrm.sv	Fix Issue 145	2023-03-22 04:33:14 -07:00
csrs.sv	Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0	2023-03-22 04:41:57 -07:00
csrsr.sv	Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.	2023-02-16 07:37:12 -08:00
csru.sv	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-02-03 08:36:11 -08:00
privdec.sv	Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.	2023-02-21 09:32:17 -08:00
privileged.sv	Fix Issue 145	2023-03-22 04:33:14 -07:00
privmode.sv	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
privpiperegs.sv	Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.	2023-02-21 09:32:17 -08:00
trap.sv	Added csr write counter, sfence vma counter, interrupt counter, and exception counter.	2023-03-02 23:21:29 -06:00