Github_Repos/cvw
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209 Commits

Author SHA1 Message Date
Kevin Kim
5056eb404c formatting 2023-03-20 13:09:49 -07:00
Kevin Kim
82d52f892b Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-20 13:06:10 -07:00
Kevin Kim
b394e343f6 format + min/max structural mux 2023-03-20 09:37:57 -07:00
David Harris
6922298f21 Replaced FenceM with InvalidateICacheM for event counting of fence.i 2023-03-18 09:24:31 -07:00
Kevin Kim
0d0d3b981e more checks in bitmanip decode 2023-03-10 17:17:24 -08:00
Kevin Kim
9b4f3219db formatting 2023-03-10 14:32:01 -08:00
Kevin Kim
c380b0816d removed redundant convinvb signal 2023-03-10 14:18:24 -08:00
Kevin Kim
dcaf9de228 removed redundant condinvb mux 2023-03-10 14:17:38 -08:00
David Harris
33fa7e4706 Simplified SLT and SLTU code in ALU 2023-03-09 15:14:52 -08:00
Kevin Kim
f29e8932a2 more comprehensive illegal b instr. check 2023-03-09 12:44:51 -08:00
Kevin Kim
f335d08bbf fixed bmu bug 
- accidentally deleted count instruction decode
 2023-03-09 12:35:42 -08:00
Kevin Kim
7002221dec cleaner bmu decode logic 2023-03-08 16:22:43 -08:00
Kevin Kim
0ca530fffd Merge branch 'bit-manip' into illegal_specific 2023-03-07 14:07:59 -08:00
Kevin Kim
4bb43892f9 alu formatting 2023-03-07 14:01:47 -08:00
Kevin Kim
26cb1857f3 specifc instruction handling for B's 
- Added BALUSrcBD, BaseALUSrcB for distinguishing between base instruction I/IW and Bitmanip instruction I/IW
 2023-03-07 13:58:08 -08:00
Kip Macsai-Goren
2ec3c741ef Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip 2023-03-07 13:44:51 -08:00
Kip Macsai-Goren
f178c90c02 Merge branch 'main' of github.com:kipmacsaigoren/cvw into bit-manip 2023-03-07 13:44:19 -08:00
Kevin Kim
bd9b9970f5 Merge remote-tracking branch 'origin' into illegal_specific 2023-03-07 11:30:36 -08:00
Kevin Kim
6d146a7e20 formatting 2023-03-07 10:57:52 -08:00
Kevin Kim
833e7bd2af shifter sign generation logic optimize 2023-03-07 10:57:06 -08:00
Kevin Kim
81198ce6f6 reverted backing to working version 2023-03-07 00:29:58 -08:00
Kevin Kim
5637897dce reverted to working version 2023-03-07 00:28:07 -08:00
David Harris
7ecf4cdea8 Fixed bug about rv64 shifts only using 6 bits of funct7 2023-03-06 13:10:51 -08:00
David Harris
7e0c96cdcc Simplified decoder default to illegal instruction 2023-03-06 11:21:11 -08:00
David Harris
c2efdbdbbb More detailed decoding of load/store/branch/jump 2023-03-06 11:15:48 -08:00
David Harris
a56557d847 Improved decoding illegal instructions in controller 2023-03-06 11:02:42 -08:00
Kevin Kim
c7d1e35d4a structural changes in cnt.sv 2023-03-06 06:44:15 -08:00
Kevin Kim
e67b02136c formatting 2023-03-06 06:20:25 -08:00
Kevin Kim
ee66b5fb4a formatting 
- reverted back to ALUResult signal in alu.sv
 2023-03-06 06:19:01 -08:00
Kevin Kim
8f3acedec8 formatted files 2023-03-06 05:52:08 -08:00
Kevin Kim
fb529e1640 updated license header 2023-03-06 05:41:53 -08:00
Kevin Kim
e80c1248a2 bug fix 2023-03-05 15:20:48 -08:00
Kevin Kim
3dbdf3d579 extend unit structural mux 2023-03-05 15:09:02 -08:00
Kevin Kim
696cfb6949 zbb result select mux structural 2023-03-05 14:57:30 -08:00
Kevin Kim
2ae32f75b5 zbc input mux structural 2023-03-05 14:26:31 -08:00
Kevin Kim
77d8f10574 revA signals to cnt, zbb 2023-03-05 14:26:24 -08:00
Kevin Kim
7836bc1e37 ALU changes 
- added PreShiftAmt signal for shadd
- condinvB now muxes from B instead of mask
 2023-03-05 14:06:24 -08:00
Kevin Kim
0f2360f0d7 bug in bctrl 
- deleted the min/minu decoding for some reason.
 2023-03-04 23:56:33 -08:00
Kevin Kim
6b25c64a1f BSelect from OH encoding to Binary 2023-03-04 23:19:31 -08:00
Kevin Kim
a293c350ba alu pre-shift 
-changed ALU pre shift logic to use a 2 bit shifter instead of mux
 2023-03-04 23:07:06 -08:00
Kevin Kim
7512e55699 added python script 
-I've been using this python script to make quick changes to the bitmanip controller
 2023-03-04 22:54:32 -08:00
Kevin Kim
9494cf9340 removed rotate signal in datapath and instead packed into the new BALUControl Signal 
- BALUControl contains Rotate, Mask, PreShift signals to select from the respective generation muxes in the ALU
 2023-03-04 22:44:03 -08:00
Kevin Kim
f5dca0bf4f zbc result mux is now structural 2023-03-04 09:22:21 -08:00
Kevin Kim
72de867e65 Rotate signal now gets generated in bmu ctrl 2023-03-03 22:57:49 -08:00
Kevin Kim
b315066b03 license comments 2023-03-03 21:52:34 -08:00
Kevin Kim
0403cfd41a removed redundant signals in controller 2023-03-03 21:52:25 -08:00
Kevin Kim
8dd39fbcfb b controller generates comparison signed flag and controller branch signed logic updated accordingly 2023-03-03 17:12:29 -08:00
Kevin Kim
5e01f86bc5 sltD signal debug. Passes regression 2023-03-03 12:44:33 -08:00
Kevin Kim
c836eea17c sltD logic optimize 2023-03-03 12:35:40 -08:00
Kevin Kim
d6f8c1dd29 Merge branch 'bctrlmigrate' of https://github.com/kipmacsaigoren/cvw into bctrlmigrate 2023-03-03 09:54:08 -08:00
Kevin Kim
1c55d4a8d5 Merge branch 'openhwgroup:main' into bctrlmigrate 2023-03-03 09:53:59 -08:00
Kevin Kim
422b428cba removed outdated b-signals in controller 2023-03-03 08:45:42 -08:00
Kevin Kim
9cad890c1a comments to bctrl 2023-03-03 08:41:47 -08:00
Kevin Kim
19410b4196 migrated B-subarith logic into b controller 2023-03-03 08:40:29 -08:00
Kevin Kim
2c3271dd62 began subarith configurability optimization in controller 2023-03-03 08:27:11 -08:00
Ross Thompson
cfca77172e Added fence counter. 2023-03-02 23:29:20 -06:00
Kevin Kim
b21ca2fba0 bug fix, more elegant logic changes in controller 2023-03-02 16:00:56 -08:00
Kevin Kim
c9bd37c92b formatting 2023-03-02 15:28:43 -08:00
Kevin Kim
910eeea3ff removed main instruction decoder dependence on bmu controller 2023-03-02 15:28:33 -08:00
Kevin Kim
05b329dd6a added bitmanip illegal instruction signal 2023-03-02 15:09:55 -08:00
Kevin Kim
3e8e633a56 zbc comments 2023-03-02 13:52:00 -08:00
Kevin Kim
b0307f5082 formatted bmu decoder 2023-03-02 13:45:15 -08:00
Kevin Kim
24b0b83d52 moved ALUControlD into configurable block 2023-03-02 12:17:03 -08:00
Kevin Kim
0f60505179 moved SubArith and RegWriteE into configurable block 2023-03-02 12:15:57 -08:00
Kevin Kim
b81a5e4452 added BRegWriteE signal 2023-03-02 12:15:22 -08:00
Kevin Kim
5e10720bed rename shifternew to shifter 2023-03-02 11:45:32 -08:00
Kevin Kim
cf324510f3 zbc input select mux optimize 2023-03-02 11:43:05 -08:00
Kevin Kim
657719220a zbc select mux optimization 2023-03-02 11:40:29 -08:00
Kevin Kim
e62a752522 fixed controller lint, changed byte unit mux select name and input width 2023-03-02 11:36:12 -08:00
Kevin Kim
a5e2e24320 removed redundant zbs 2023-03-02 11:22:09 -08:00
Kip Macsai-Goren
58ab6ec805 Merge remote-tracking branch 'upstream/main' into bit-manip 2023-02-28 14:41:51 -08:00
Kevin Kim
df0d75034b bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG] 2023-02-28 12:09:35 -08:00
Kevin Kim
b61d881c1b added BRegWrite, BW64, BALUOp signals to bctrl and controller 
-TODO: Main decode in bmuctrl must assert these 3 signals
 2023-02-28 11:54:10 -08:00
Kevin Kim
692e406976 changed shifter source select signal name 2023-02-28 11:41:40 -08:00
Kevin Kim
1506d50c63 rename result back to ALUResult in ALU 2023-02-28 07:27:34 -08:00
David Harris
cf8b5f0783 Added support for ZMMUL 2023-02-27 07:29:53 -08:00
Kevin Kim
f5d3e0e8a0 removed old shifter 2023-02-24 17:33:47 -08:00
Kevin Kim
601c6fcdc4 removed now-redundant zero-extend mux in alu 2023-02-24 17:14:12 -08:00
Kevin Kim
1d4200e3a3 took sign extension out of shifter 2023-02-24 17:09:56 -08:00
Kevin Kim
00a0170b30 optimized mux to shifter, passes rv32/64i 2023-02-24 12:09:34 -08:00
Kevin Kim
8b6d699857 small optimization to condzext select 2023-02-23 21:57:28 -08:00
Kip Macsai-Goren
67f83cda7f Fixed lint errors on zero and pop count. All of regression passes 2023-02-22 20:25:51 -08:00
Kip Macsai-Goren
ba3bfdf68b Manual attempt to merge with upstream changes 2023-02-22 19:42:30 -08:00
Kip Macsai-Goren
d668c563f4 Merge remote-tracking branch 'upstream/main' into main 2023-02-21 14:48:41 -08:00
Kevin Kim
35bd4f7219 added individual zb tests in tests.vh and testbench 
- also minor alu/controller configurability changes
 2023-02-21 11:52:05 -08:00
David Harris
a445e53e8d Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well. 2023-02-21 09:32:17 -08:00
Kevin Kim
0f876c3111 B DONE (for now) 
- datapath passes along comparator flag to alu
-  controllers and zbb handle min/max instructions
 2023-02-18 22:12:55 -08:00
Kevin Kim
2319661b10 controlleres and zbb handle byte instructions 2023-02-18 21:06:55 -08:00
Kevin Kim
e7339902ae alu and controllers handle andn, orn, xnor 2023-02-18 20:57:07 -08:00
Kevin Kim
59e9c7c747 added logic to handle sign/zero extend instructions 2023-02-18 20:32:40 -08:00
Kevin Kim
ad63699aac fixed ctlzw bug in count unit 2023-02-18 20:12:30 -08:00
Kevin Kim
ecfcad20a0 zbb handles count instructions 2023-02-18 20:12:17 -08:00
Kevin Kim
543dc1e36a fixed bmuctrl decode bug 2023-02-18 20:11:50 -08:00
Kevin Kim
446327215d updated comments in bmuctrl 2023-02-18 19:57:10 -08:00
Kevin Kim
baff2c9362 rotate instructions now handled in ZBB unit 2023-02-18 19:56:54 -08:00
Kevin Kim
e4085764e7 removed redundant decode logic in bmuctrl 2023-02-18 19:50:36 -08:00
Kevin Kim
f18cd53dee began ZBB integration into ieu 2023-02-18 19:44:14 -08:00
Kevin Kim
5f56f72bb1 bmuctrl handles roriw 2023-02-18 16:26:16 -08:00
Kevin Kim
2ccbde9d09 configured shifter in alu 2023-02-17 21:58:49 -08:00
Kevin Kim
f85c1058ff shifter bug fix 
- roli not passing unless I keep the MSB (instead of inverting) of truncated offset
 2023-02-17 21:58:26 -08:00