bbracker
7852d866ef
JALR testing
2021-03-04 10:37:30 -05:00
Teo Ene
d3a1afe50e
Fix to last push
2021-03-03 15:20:38 -06:00
David Harris
6f4e8b723e
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
David Harris
38b8cc652c
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
David Harris
7737b0f709
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8
Debugging Bus interface
2021-02-22 13:48:30 -05:00
David Harris
a7dd20b388
Multiply instructions working
2021-02-17 15:29:20 -05:00
David Harris
adc5d5bc1a
Added MUL
2021-02-15 22:27:35 -05:00
Domenico Ottolia
3ee975dd5a
Add privileged test cases
2021-02-14 17:01:46 -05:00
Shreya Sanghai
4e887f83a3
added branch tests
2021-02-12 22:40:08 -05:00
bbracker
deb7780897
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Tejus Rao
fb6a4bbbf0
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
5f84ed407c
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
ethan-falicov
7925fe3131
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
06517631cc
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
863796b3c1
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
67662b888e
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
David Harris
b121b90b28
Debugging bus interface.
2021-02-10 01:43:54 -05:00
David Harris
842c374de9
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
Jarred Allen
e334475ab5
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
805817cda4
merge conflict?
2021-02-07 02:34:49 -05:00
Jarred Allen
29b7a0cd25
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
bbracker
15c0b4af22
JAL testing
2021-02-05 08:08:42 -05:00
Thomas Fleming
8d7a515ae7
Complete STORE tests
2021-02-04 15:38:22 -05:00
Noah Boorstin
f1768ee50b
Busybear: start checking CSRs
...
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)
and 3 of the CSRs referenced are skipped because of weird locations for them
oh and this doesn't check their initial state, just their changing. This could be a problem
2021-02-02 06:06:03 +00:00
Noah Boorstin
38265c03b7
busybear: start adding CSR checking
...
@kaveh is there a less verbose way to do this?
2021-02-01 22:08:51 -05:00
Noah Boorstin
d592db79c9
busybear: change register file checking to only store register changed
...
this should make parsedRegs.txt much smaller
2021-02-02 01:27:43 +00:00
Noah Boorstin
71f5bb0ce8
Add PCW checking
...
for now, doesn't check InstrW because it fails on compressed instructions
2021-02-01 23:57:33 +00:00
Noah Boorstin
1b9ec8b339
busybear: print warning when NOPing out instructions
2021-02-01 19:44:56 +00:00
Noah Boorstin
a82f8977c6
busybear: NOP out floating point instructions for now
...
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
2021-01-30 19:52:47 +00:00
Noah Boorstin
cca60ed06d
update busybear testbench to conform to new structure
...
aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
David Harris
26c560fba3
Added HCLK and HRESETn
2021-01-30 00:56:12 -05:00
David Harris
9511dcac84
Connected AHB bus to Uncore
2021-01-29 23:43:48 -05:00
David Harris
6d5b01357d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 15:38:01 -05:00
David Harris
d104e5a4be
Moving data memory to uncore
2021-01-29 15:37:51 -05:00
Noah Boorstin
7183910c84
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
David Harris
4687d6998a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 01:07:22 -05:00
David Harris
e4e95bf941
Added ahblite bus interface unit
2021-01-29 01:07:17 -05:00
Noah Boorstin
84e4193db6
busybear testbench: test on first 100k instrs
...
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
2021-01-29 00:14:23 -05:00
Noah Boorstin
c4964352f0
busybear: simulate first 10k instructions
...
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
2021-01-28 19:44:58 -05:00
Noah Boorstin
96ceac0e80
busybear: fix misaligned writing checking
2021-01-28 19:35:09 -05:00
Noah Boorstin
df1d174aea
busybear: add more test instructions
...
currently testing first 1k instrs
2021-01-28 16:41:37 -05:00
Noah Boorstin
9c0580f2e1
oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench
2021-01-28 16:35:12 -05:00
Noah Boorstin
e65166bec5
busybear testbench: understand bytemask for writes
2021-01-28 15:42:47 -05:00
Noah Boorstin
9a45b49536
busybear: ret is only 1 word
2021-01-28 14:47:40 -05:00
