91 Commits

Author	SHA1	Message	Date
David Harris	05aa18fe14	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
David Harris	129fab3794	Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.	2022-06-02 14:18:55 +00:00
David Harris	31815422d2	../src/privileged/csrc.sv	2022-05-31 21:12:17 +00:00
David Harris	2935188035	Moved delegation logic from privmode to trap to simplify interface	2022-05-31 14:58:11 +00:00
Ross Thompson	9079e67aae	Updated fpga debugger.	2022-05-17 23:04:01 -05:00
David Harris	f5e2cff45a	Cause simplification	2022-05-12 23:47:21 +00:00
David Harris	6303d4e81f	Cause simplification	2022-05-12 23:39:10 +00:00
David Harris	c4621c5b6b	Cause simplification	2022-05-12 23:37:40 +00:00
David Harris	7daf631c13	Cause simplification	2022-05-12 23:33:35 +00:00
David Harris	de51c7eeb3	Cause simplification	2022-05-12 23:33:22 +00:00
David Harris	803bfc4fe4	Cause simplification	2022-05-12 23:29:35 +00:00
David Harris	2d27d20db9	Cause simplification	2022-05-12 23:27:02 +00:00
David Harris	87dadc8208	trap/csr cleanup	2022-05-12 22:26:21 +00:00
David Harris	ea0d9fd9a8	More trap/csr simplification	2022-05-12 22:06:03 +00:00
David Harris	2eb6a65fa2	More trap/csr simplification	2022-05-12 22:04:20 +00:00
David Harris	2d8ccbd4ea	More trap/csr simplification	2022-05-12 22:00:23 +00:00
David Harris	417e36bff5	More trap/csr simplification	2022-05-12 21:55:50 +00:00
David Harris	ca6b7716e2	Simplifying trap/csr interface	2022-05-12 21:50:15 +00:00
David Harris	56c154f2e7	Simplified MTVAL logic	2022-05-12 21:36:13 +00:00
David Harris	730bcac6ba	Partitioned privileged pipeline registers into module	2022-05-12 20:45:45 +00:00
David Harris	c5868b81e4	privileged cleanup	2022-05-12 20:21:33 +00:00
David Harris	5537c33196	Formatting cleanup	2022-05-12 18:37:47 +00:00
David Harris	449472ba58	Moved Breakpoint and Ecall fault logic into privdec	2022-05-12 16:45:53 +00:00
David Harris	9f8dca5190	Moved TLB Flush logic into privdec	2022-05-12 16:41:52 +00:00
David Harris	1d01bc98a4	Moved WFI timeout into privdec	2022-05-12 16:22:39 +00:00
David Harris	21c1e58829	Partitioned privilege mode fsm into new module	2022-05-12 16:16:42 +00:00
David Harris	5acb526375	More unused signal cleanup	2022-05-12 15:21:09 +00:00
David Harris	7e764fbda1	More unused signal cleanup	2022-05-12 15:15:30 +00:00
David Harris	e2dea3bb89	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	fb725a9e0a	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	15659b05e4	Simplifed mstatus.TSR handling	2022-05-12 14:09:52 +00:00
David Harris	877c4eefd1	Fixed typo in csrm	2022-05-12 06:55:39 -07:00
David Harris	32f8841f79	Added MCONFIGPTR CSR hardwired to 0	2022-05-12 04:31:45 +00:00
David Harris	a8c9f504fa	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	91472eb948	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	8066ba45e8	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	2792d77e4e	Fixed bug in delegated interrupts not being taken	2022-05-08 04:50:27 +00:00
David Harris	2cdd49c7d2	WFI terminates when an interrupt is pending even if interrupts are globally disabled	2022-05-08 04:30:46 +00:00
David Harris	66424a8246	SFENCE.VMA should be illegal in user mode	2022-05-05 15:15:02 +00:00
David Harris	866540580a	SFENCE.VMA should be illegal in user mode	2022-05-05 14:59:52 +00:00
David Harris	c100c9893b	wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts	2022-05-05 14:37:21 +00:00
David Harris	94459ade3d	Changed WFI to stall pipeline in memory stage	2022-05-05 02:03:44 +00:00
David Harris	554c2b3550	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
David Harris	9c4de0e9c1	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
Kip Macsai-Goren	8ad920fcb3	fixed initial value, timing on fs bits changing after floating point instruction	2022-04-25 19:17:29 +00:00
David Harris	cf1fde62fb	Restored MPRV behavior per spec	2022-04-25 14:52:18 +00:00
David Harris	0ede295e88	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
David Harris	851d5e8c5e	Added MTINST hardwired to 0, and added timeout of U-mode WFI	2022-04-24 20:00:02 +00:00
David Harris	16ad1e0cab	Fixed InstrMisalignedFaultM mtval	2022-04-24 17:31:30 +00:00
David Harris	f1ddbb169c	Improved priority order and mtval of traps to match spec	2022-04-24 17:24:45 +00:00