cvw/pipelined/src/privileged
2022-05-08 04:50:27 +00:00
..
csr.sv SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
csrc.sv Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
csri.sv Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
csrm.sv Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
csrs.sv Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change. 2022-02-15 19:20:41 +00:00
csrsr.sv FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
csru.sv Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
privdec.sv SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
privileged.sv WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
trap.sv Fixed bug in delegated interrupts not being taken 2022-05-08 04:50:27 +00:00