cvw/pipelined/src/privileged
2022-05-08 06:46:35 +00:00
..
csr.sv Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
csrc.sv Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
csri.sv Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
csrm.sv Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
csrs.sv Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change. 2022-02-15 19:20:41 +00:00
csrsr.sv Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
csru.sv Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
privdec.sv SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
privileged.sv Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
trap.sv Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00