David Harris
4740ef97d6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-07 16:14:13 -04:00
David Harris
c3d21967f8
Simplified superpage matching
2021-06-07 16:11:28 -04:00
Katherine Parry
b55798f09b
lint is clean
2021-06-07 14:22:54 -04:00
bbracker
3e11da2aa2
temporarily removing buildroot from regression until it is regenerated
2021-06-07 13:20:50 -04:00
David Harris
b37bcc8e38
Continued merge
2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
David Harris
95cc70295b
Merge difficulties
2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d
Refactored configuration files and renamed testbench-busybear to testbench-linux
2021-06-07 09:46:52 -04:00
Katherine Parry
e4db6ea6f5
fixed lint warnings for fpu and lzd
2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
d69501c4fa
Cleaned up some unused signals
2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
b99b5f8e0e
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
Kip Macsai-Goren
4a00fbaf04
Merge branch 'mmu' into main
...
new mmu unit and moving pmp/pma now passes regression except for lint and buildroot
2021-06-04 17:07:56 -04:00
Kip Macsai-Goren
318a547531
added shared constants file list of includes
2021-06-04 17:05:47 -04:00
Kip Macsai-Goren
7e41b17e65
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
Ross Thompson
6f58c66be8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-04 15:16:39 -05:00
Ross Thompson
e200b4b5a4
Continued I-Cache cleanup.
...
Removed strange mux on InstrRawD along with
the select logic.
2021-06-04 15:14:05 -05:00
Ross Thompson
35afdecda2
Moved I-Cache offset selection mux to icache.sv (top level).
...
When we switch to set associative this is will be more efficient.
2021-06-04 13:49:33 -05:00
Ross Thompson
fdc7c673dd
Cleaned up the I-Cache memory.
2021-06-04 13:36:06 -05:00
Katherine Parry
19116ed889
Double-precision FMA instructions
2021-06-04 14:00:11 -04:00
Ross Thompson
2c16591396
Reorganized the icache names.
2021-06-04 12:53:42 -05:00
Ross Thompson
147be536f1
Relocated the icache to the cache directoy.
2021-06-04 12:23:46 -05:00
David Harris
b836679ae1
Started MMU
2021-06-04 11:59:14 -04:00
David Harris
99d661cee9
Fixed RV32 MMU constants
2021-06-04 09:15:42 -04:00
David Harris
a61411995a
moved shared constants to a shared directory
2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
1b2822e078
added support for sv48 and some docs on how to use these files
2021-06-03 14:32:12 -04:00
Kip Macsai-Goren
a84dd6dfc5
added tests for SV48 and translation off with vmem
2021-06-03 14:28:52 -04:00
bbracker
d8913e5547
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-03 10:03:26 -04:00
bbracker
8338b3bd34
expanded GPIO testing and caught small GPIO bug
2021-06-03 10:03:09 -04:00
Ross Thompson
db2a38c300
Fixed a few lint errors,
...
clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
bbracker
4f03ecb6ec
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-02 10:03:23 -04:00
bbracker
28abd28b1f
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
Kip Macsai-Goren
f7deda0514
implemented Sv48.
2021-06-01 17:50:37 -04:00
Kip Macsai-Goren
06cf3a8403
Edited and added constants to support SV48
2021-06-01 17:49:45 -04:00
James E. Stine
7f5e5287b0
delete div.bak
2021-06-01 17:39:54 -04:00
Ross Thompson
2093e7cce3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 15:20:37 -05:00
Ross Thompson
7afbd8d877
The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
2021-06-01 15:05:22 -05:00
James E. Stine
2c140679e3
Minor cosmetic update to fpu.sv
2021-06-01 15:45:32 -04:00
James E. Stine
bccdd2c137
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 15:31:07 -04:00
Ross Thompson
8e330367ac
added clock gater to floating point divider to speed up simulation time.
2021-06-01 13:46:21 -05:00
Ross Thompson
605ceb7ddb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 12:42:21 -05:00
Ross Thompson
f5aa5d7c67
Forgot to include the new gshare predictor file.
2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
8f7e69715d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-01 13:20:39 -04:00
Ross Thompson
9a49cf74c3
Changed to bp config to use gshare.
2021-06-01 12:14:58 -05:00
Ross Thompson
8f9680556f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2
Modify muldiv.sv to handle W instructions for 64-bits
2021-05-31 23:27:42 -04:00
Ross Thompson
1db8d0e59c
may have fixed the global branch history predictor.
...
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
42af5f9818
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-31 11:01:15 -04:00
James E. Stine
a71b97e878
Cosmetic changes on integer divider
2021-05-31 09:16:30 -04:00
James E. Stine
2f365a9e07
Add enhancements to integer divider including:
...
- better comments
- optimize FSM to end earlier
- passes for 32-bit or 64-bit depending on parameter to intdiv
Left div.bak in just in case have to revert back to original for now.
2021-05-31 09:12:21 -04:00
