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4084a11350
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Author SHA1 Message Date
Jacob Pease
4084a11350 Adjusted the new makefile. 2023-08-02 16:24:20 -05:00
Jacob Pease
064e863476 Buildroot can now be set up with the new Linux Makefile. The driver can now also be loaded from addins/vivado-risc-v and should be removed from the main Wally repo. A sed command customizes the package source location for the new buildroot directory. 2023-08-02 16:12:26 -05:00
Jacob Pease
e0a63f79ce Removed duplicate line in Makefile. 2023-08-02 14:59:20 -05:00
Jacob Pease
7c1d7b07bb Linux makefile now copies the package contents with the correct package source. 2023-08-02 14:56:23 -05:00
Jacob Pease
068a0d10fd Added a Makefile to the Linux directory to take care of the Buildroot setup and other dependencies. 2023-08-02 14:28:17 -05:00
Ross Thompson
7cf340f6eb Merge pull request #376 from JacobPease/main 
Updated driver for latest version of linux
 2023-08-01 13:57:08 -04:00
Jacob Pease
337f5fadc7 Updated driver for latest version of linux 2023-08-01 12:56:16 -05:00
Ross Thompson
66b97ad812 Merge pull request #375 from JacobPease/main 
Updated Linux and Buildroot versions
 2023-08-01 11:57:55 -04:00
Jacob Pease
3deff32639 Updated linux and buildroot configs initial commit. 2023-08-01 10:55:46 -05:00
Jacob Pease
19287defe5 Merge branch 'main' of github.com:openhwgroup/cvw 2023-08-01 10:47:59 -05:00
Ross Thompson
faaf43fa10 Merge pull request #372 from davidharrishmc/dev 
PLIC part select warnings fixed
 2023-07-31 11:28:28 -04:00
David Harris
6ff2b0cc2c Merge pull request #373 from harshinisrinath1001/main 
Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
 2023-07-30 22:46:44 -07:00
Harshini Srinath
7ed4cf97ed Fixed formatting 2023-07-30 18:36:25 -07:00
Harshini Srinath
603ed2160e Fixed formatting 2023-07-30 18:30:23 -07:00
Harshini Srinath
7e201d1e8c Fixed formatting 2023-07-30 18:28:27 -07:00
Harshini Srinath
acbbe7941a Fixed formatting 2023-07-30 18:27:22 -07:00
Harshini Srinath
7e237858a0 Fixed formatting 2023-07-30 18:20:38 -07:00
Harshini Srinath
e4de9ae87c Fixed formatting 2023-07-30 18:18:24 -07:00
Harshini Srinath
4c1a07eb9c Fixed formatting 2023-07-30 18:06:25 -07:00
Harshini Srinath
1badc8a8c5 Fixed formatting 2023-07-30 18:00:39 -07:00
Harshini Srinath
41555b149e Fixed formatting 2023-07-30 17:54:47 -07:00
Harshini Srinath
8e97224cd7 Fixed formatting 2023-07-30 17:46:23 -07:00
Harshini Srinath
469b03577d Fixed formatting 2023-07-30 17:39:37 -07:00
Harshini Srinath
141384f60f Fixed formatting 2023-07-30 17:38:22 -07:00
Harshini Srinath
bbbd5f6b2d Fixed spacing 2023-07-30 17:32:46 -07:00
Harshini Srinath
d7b2d84124 Fixed spacing 2023-07-30 17:22:40 -07:00
Harshini Srinath
b129068a92 Fixed spacing 2023-07-30 17:21:52 -07:00
Harshini Srinath
49823ccd45 Fixed spacing 2023-07-30 17:21:22 -07:00
Harshini Srinath
36108e4b52 Fixed spacing 2023-07-30 17:18:25 -07:00
Harshini Srinath
d88b2fd9c1 Fixed spacing 2023-07-30 16:59:27 -07:00
Harshini Srinath
d69d0ececc Fixed spacing 2023-07-30 16:57:57 -07:00
harshinisrinath
b4cfdf3393 Fixed bug and tried to reset menvcfg to improve testing of csri in priv. 2023-07-30 16:40:06 -07:00
David Harris
d58ece3d44 renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
David Harris
28823aca6e Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
654cafb7f7 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Jacob Pease
df6db12bbe Merge branch 'main' of github.com:openhwgroup/cvw 2023-07-28 12:49:19 -05:00
David Harris
b47ce62a97 Merge pull request #371 from ross144/main 
Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv.  STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop.
 2023-07-28 09:51:58 -07:00
Ross Thompson
c216f6c014 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-28 11:23:17 -05:00
Ross Thompson
7e06775135 Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Jacob Pease
55055aa0a8 Updated VCU108 device tree for 256MB memory. 2023-07-27 17:44:31 -05:00
Ross Thompson
aa48246778 Merge pull request #370 from JacobPease/main 
Fixed GPIO pin names in fpgaTop.v
 2023-07-27 16:10:44 -04:00
Jacob Pease
9d33e08dbb Removed non-existent SDC dependency from VCU targets in FPGA Makefile. 2023-07-27 15:01:20 -05:00
Jacob Pease
81c6b7e05e Merge branch 'main' of github.com:openhwgroup/cvw 2023-07-27 14:46:01 -05:00
David Harris
8218d806bd Merge pull request #369 from ross144/main 
Fixed issue #368 lint, but not simulation
 2023-07-26 13:32:02 -07:00
Ross Thompson
15dc76310e Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Jacob Pease
b626f2185a Fixed GPIO pin names in fpgaTop.v 2023-07-25 20:57:04 -05:00
David Harris
1f35023757 Merge pull request #367 from ross144/main 
Complete removal of old flash card hardware and updates to Arty A7 to push clock speed to 20Mhz and increase memory to 256 MiB
 2023-07-25 15:26:08 -07:00
Ross Thompson
2dac02c14c Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
Ross Thompson
dbf9e5da0b Updated Arty A7 fpga config and device tree to 256MiB main memory. 2023-07-25 15:11:47 -05:00
Ross Thompson
e3bcf10185 Merge pull request #366 from davidharrishmc/dev 
Progress toward DC synthesis
 2023-07-25 11:39:49 -04:00