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https://github.com/openhwgroup/cvw
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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commit
c216f6c014
@ -24,7 +24,7 @@ all: FPGA_Arty
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FPGA_Arty: PreProcessFiles IP_Arty
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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FPGA_VCU: PreProcessFiles IP_VCU SDC
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FPGA_VCU: PreProcessFiles IP_VCU
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
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@ -421,8 +421,8 @@ module fpgaTop
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wire [3:0] sd_dat_reg_o;
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wire sd_dat_reg_t;
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assign GPIOPinsIn = {28'b0, GPI};
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assign GPO = GPIOPinsOut[4:0];
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assign GPIOIN = {28'b0, GPI};
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assign GPO = GPIOOUT[4:0];
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assign ahblite_resetn = peripheral_aresetn;
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assign cpu_reset = bus_struct_reset;
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assign calib = c0_init_calib_complete;
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