bbracker
5022647041
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit f6ef8e5656
2021-09-30 20:45:26 -04:00
bbracker
f6ef8e5656
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
David Harris
654f3d1940
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
bbracker
5e9a39e755
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
Ross Thompson
bb3e94d68a
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
Ross Thompson
97653e1aea
Wally previously was overcounting retired instructions when they were flushed.
...
InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
b6e2710f5d
Confirmed David's changes to the interrupt code.
...
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
David Harris
696be3ff68
possible interrupt code
2021-08-22 17:02:40 -04:00
Ross Thompson
4f3f26c5cb
Switched ExceptionM to dcache to be just exceptions.
...
Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
d430659983
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Kip Macsai-Goren
bb8ec549a7
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
ae2371f2ce
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
bbracker
77b690faf0
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
David Harris
e3bf8db80b
trap.sv comment cleanup
2021-07-17 16:01:07 -04:00
David Harris
b2c2194478
trap.sv cleanup
2021-07-17 15:57:10 -04:00
David Harris
348e69c096
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:24:26 -04:00
David Harris
49ec45d04d
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:22:24 -04:00
Ross Thompson
4549a9f1c9
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
e17de4eb11
Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
...
This solves the committedM issue.
2021-07-14 15:00:33 -05:00
Katherine Parry
b9edbb15eb
Fixed writting MStatus FS bits
2021-07-13 13:22:04 -04:00
Katherine Parry
acdd2e4504
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
David Harris
68d1f87101
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
David Harris
b09fd0d0a8
Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
David Harris
4d53a935b3
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
David Harris
78850bfcd8
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
2021-07-06 15:29:42 -04:00
Ross Thompson
dc4c26d2a2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-06 13:45:20 -05:00
Ross Thompson
d85bf23af3
Merged several of the load/store/instruction access faults inside the mmu.
...
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
2021-07-06 13:43:53 -05:00
Abe
79e62b7c53
Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140)
2021-07-06 12:37:58 -04:00
David Harris
6785ed9994
Implemented TSR, TW, TVM, MXR status bits
2021-07-06 01:32:05 -04:00
David Harris
3cb9e5acd3
Fixed adrdecs to use Access signals for TIMs
2021-07-05 23:42:58 -04:00
David Harris
8ca7abaa02
Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
2021-07-05 20:35:31 -04:00
David Harris
57e1111df3
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
a5c0dc8c81
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
b5df9b282d
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
David Harris
4ec570d2d7
Fixed PMPCFG read faults
2021-07-02 17:08:13 -04:00
David Harris
648c09e5ef
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
bbracker
ced5039776
Revert "fixed forwarding"
...
This reverts commit 0f4a4a6ade
2021-06-24 17:39:37 -04:00
bbracker
0f4a4a6ade
fixed forwarding
2021-06-24 11:20:21 -04:00
David Harris
aef408af58
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
0a59b006ab
Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
2021-06-20 22:59:04 -04:00
bbracker
83a1f29c37
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
bbracker
7aa2f0d953
make xCOUNTEREN what buildroot expects it to be
2021-06-20 09:22:31 -04:00
David Harris
e03912f64c
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
bbracker
076469230f
added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version
2021-06-17 12:09:10 -04:00
bbracker
db0abfd36d
enable TIME CSR for 32 bit mode as well
2021-06-17 11:34:16 -04:00
bbracker
7d1469a06c
provide time and timeh CSRs based on CLINT's counter
2021-06-17 08:38:30 -04:00
bbracker
0647094e73
PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable
2021-06-17 05:19:36 -04:00
bbracker
7a652139b5
mcause test fixes and s-mode interrupt bugfix
2021-06-16 17:37:08 -04:00
David Harris
79ee817d91
Reverted MIDELEG and MEDELEG to XLEN so busybear passes
2021-06-10 23:47:32 -04:00
