cvw/wally-pipelined/src/privileged
2021-07-17 15:22:24 -04:00
..
csr.sv Fixed writting MStatus FS bits 2021-07-13 13:22:04 -04:00
csrc.sv Fixed InstrValid from W to M stage for CSR performance counters 2021-07-13 13:19:13 -04:00
csri.sv Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
csrm.sv Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 13:45:20 -05:00
csrn.sv Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
csrs.sv Simplified tlbmixer mux to and-or 2021-07-08 23:34:24 -04:00
csrsr.sv Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
csru.sv Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
privdec.sv Implemented TSR, TW, TVM, MXR status bits 2021-07-06 01:32:05 -04:00
privileged.sv hptw: Removed NonBusTrapM from LSU 2021-07-17 15:22:24 -04:00
trap.sv hptw: Removed NonBusTrapM from LSU 2021-07-17 15:22:24 -04:00