Rose Thompson
8fb1673ab3
Updated email address authorship for my files.
2024-10-15 10:27:53 -05:00
Rose Thompson
1345a0f315
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-09-24 10:13:50 -05:00
Rose Thompson
4d56b3ca96
Maybe improvements to fpga synthesis.
2024-08-23 13:00:22 -07:00
Rose Thompson
fc80bf1251
More updates to fpga IP module names.
2024-08-22 14:31:39 -07:00
Rose Thompson
8d40a0a092
Changed names of fpga IP modules to match textbook. Updated boot.h to
...
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
2024-08-22 13:56:50 -07:00
Jacob Pease
ed0c826d74
Turned off RVVI by default.
2024-08-08 13:50:11 -05:00
Rose Thompson
7164841f83
Added padding into the hw rvvi format.
2024-08-06 18:34:46 -05:00
Jacob Pease
af2344d2d5
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
665396fdb3
SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree.
2024-08-06 16:57:57 -05:00
Jacob Pease
83b0a83d5c
Removed HSELEXTSDC and fixed SD card pin definitions.
2024-08-02 15:35:18 -05:00
Rose Thompson
d0a5b278b7
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
Rose Thompson
b1a711ae0f
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Jacob Pease
f1cc7dd5a3
Fixed verilog bugs.
2024-07-23 17:26:39 -05:00
Jacob Pease
a506d76149
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
2024-07-22 12:36:39 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
24609f0b7f
Now have configurations to switch between supporting RVVI over ethernet.
2024-07-22 10:51:13 -05:00
Rose Thompson
00840e4893
Made the fpga top level configurable between rvvi synth and not.
2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
...
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Ross Thompson
6734685333
Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.
2024-07-09 19:04:18 -05:00
Ross Thompson
ccf4bb8ddc
Maybe have the incircuit trigger working.
2024-06-26 16:15:46 -07:00
Ross Thompson
612a281f62
Added module to receive ethernet frame and trigger the ila.
2024-06-26 11:05:31 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
...
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Ross Thompson
ab1ee3d69b
Removed *** from IFU, lrcs.
2024-06-19 09:40:35 -07:00
Ross Thompson
c5dac4d775
Removed *** from fpga top.
2024-06-19 09:28:21 -07:00
Ross Thompson
47523c97ac
Getting closer to figuring out the lost ethernet frame bugs.
2024-06-13 15:46:54 -07:00
Ross Thompson
c9f51df34a
Fixed bug in rvvi reset.
2024-06-12 14:47:32 -07:00
Rose Thompson
6a4c8667df
Added new signals to ILA to debug the RVVI tracer.
...
The tracer appears to be stuck and the CPU is never getting out of (into reset).
2024-05-30 16:43:25 -05:00
Rose Thompson
9703055758
The FPGA is synthesizing with the rvvi and ethernet hardware.
2024-05-30 15:37:17 -05:00
Rose Thompson
7693c5d4e2
Updates to fpga top level.
2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388
Replaced fpga's verilog top with system verilog.
2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c
Replaced fpga top level verilog with system verilog.
2023-12-15 13:07:08 -06:00
