Jacob Pease
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2ee4525ba9
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Made minor changes to the controller to clean up the logic. Still need to simplify the first always block.
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2024-11-16 11:34:31 -06:00 |
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Jordan Carlin
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a462b9a2e6
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Clean up verilator lint off commands and remove unnecessay ones
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2024-11-15 23:52:50 -08:00 |
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Jordan Carlin
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2b57633217
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Switch to out of tree riscv-arch-test with VM tests + add pmp & vm tests to testbench
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2024-11-15 22:52:21 -08:00 |
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Jordan Carlin
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c926792941
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Update riscv-arch-test
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2024-11-15 20:24:03 -08:00 |
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David Harris
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234e47a7c5
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MTIMECMP should reset to maximum value for RV32, not just for RV64
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2024-11-15 15:37:25 -08:00 |
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David Harris
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d4852d88e2
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Merge pull request #1101 from rosethompson/main
Fixed the tracer so that traps don't clear the instruction or PC bits.
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2024-11-15 06:33:28 -08:00 |
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Rose Thompson
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fcf4ca1417
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Disabled tracer print.
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2024-11-15 08:32:43 -06:00 |
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Rose Thompson
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3596be433c
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Fixed the tracer so that traps don't clear the instruction or PC bits.
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2024-11-15 08:31:19 -06:00 |
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Rose Thompson
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fbd89eef83
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Merge pull request #1100 from davidharrishmc/dev
Fixed tracer warnings, removed fcovimp support
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2024-11-15 08:00:10 -06:00 |
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David Harris
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cb4f1bec8e
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Removed fcovimp support
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2024-11-15 05:58:30 -08:00 |
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David Harris
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c02a649c3b
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Fixed warnings related to tracer variables
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2024-11-15 05:33:16 -08:00 |
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David Harris
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d4ecaa5401
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Merge pull request #1099 from 10x-Engineers/rvvi_setup
Removing old code (not in use anymore)
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2024-11-15 04:57:29 -08:00 |
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Huda-10xe
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b2789f304a
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Removing old code (not in use anymore)
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2024-11-15 00:39:16 -08:00 |
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David Harris
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e5e592b2da
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Merge pull request #1091 from jordancarlin/rvvi32
Fix RVVI for RV32
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2024-11-14 15:33:48 -08:00 |
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Jordan Carlin
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9d2a5c6e03
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Fix wallyTracer bug
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2024-11-14 15:31:10 -08:00 |
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Jordan Carlin
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51d7eea98a
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Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi32
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2024-11-14 15:04:11 -08:00 |
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Jordan Carlin
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61c5d035e9
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Add mseccfg shell to wallyTracer and reformat CSRs
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2024-11-14 15:03:13 -08:00 |
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Jordan Carlin
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3dbfc2f9fc
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Merge pull request #1098 from rosethompson/main
Fixes issue with traps hidding instructions on rvvi interface
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2024-11-14 14:44:20 -08:00 |
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Rose Thompson
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d311ee238c
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Merge branch 'openhwgroup:main' into main
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2024-11-14 16:15:26 -06:00 |
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Rose Thompson
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5e4f4c2072
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Simple change to ensure Trapped instructions are included with rvvi as
valid instructions. Required for functional coverage.
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2024-11-14 16:14:02 -06:00 |
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Rose Thompson
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06fb807839
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Merge pull request #1096 from davidharrishmc/dev
XLEN32 support for functional coverage, restore WALLY-init-lib
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2024-11-14 15:28:20 -06:00 |
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Jordan Carlin
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60bc968b29
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Merge pull request #1097 from slmnemo/main
Fixed oversight in assertions on verilator causing nocache_rv64gc and nodcache_rv64gc to fail
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2024-11-14 12:02:37 -08:00 |
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slmnemo
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872491716d
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set ZICCLSM_SUPPORTED to 0 so that nocache_rv64gc does not fail assertion tests
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2024-11-14 12:00:45 -08:00 |
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David Harris
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4251f0c6a2
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Restored to original WALLY-init-lib beause new flavor is moved to cvw-arch-verif and the old is needed for PMP code coverage
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2024-11-14 10:56:13 -08:00 |
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David Harris
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8e6170cc83
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-11-14 08:15:44 -08:00 |
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David Harris
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054c694a27
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Fixed typo of CLINT name
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2024-11-14 08:14:56 -08:00 |
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David Harris
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eacc8c0f07
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Define XLEN32/XLEN64 in coverage configuration
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2024-11-14 08:14:22 -08:00 |
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Ahlyssa Santillana
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d41dc8d2de
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incorportated Zicsr to run in Imperas
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2024-11-14 06:26:28 -08:00 |
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David Harris
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669855ad25
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Merge pull request #1093 from AnonymousVikram/fflag_fix
Fflag Fix
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2024-11-14 04:33:58 -08:00 |
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Vikram Krishna
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0c0949e82b
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added explanation
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2024-11-14 03:54:32 -08:00 |
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Vikram Krishna
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eb777d3fa4
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updated froundnx conditional
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2024-11-14 03:53:26 -08:00 |
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Vikram Krishna
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4aecba2a51
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added handling for OpCode=100
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2024-11-14 03:51:27 -08:00 |
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Jordan Carlin
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14e9a39523
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pmps working for RVVI in RV32
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2024-11-13 22:12:11 -08:00 |
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Jordan Carlin
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d666a0dd7b
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Update formatting in an attempt to understand what's happening in this file
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2024-11-13 18:26:53 -08:00 |
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Jordan Carlin
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017b3e9872
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Fix 32 bit CSRs in wallyTracer
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2024-11-13 17:01:01 -08:00 |
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Rose Thompson
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88745e27d3
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Fixed ila after updates.
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2024-11-13 12:57:02 -06:00 |
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David Harris
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7ecd6fa991
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Merge pull request #1090 from rosethompson/lrufixes
Fixes multiple cache bugs and CacheSim.py bugs
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2024-11-13 10:32:20 -08:00 |
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Rose Thompson
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a7dd2eff01
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Switch rv64gc_CacheSim.py to use verilator as the default sim rather than questa.
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2024-11-13 12:29:02 -06:00 |
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Rose Thompson
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e22f30ec14
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Better name for CacheSetTag2.
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2024-11-13 12:24:35 -06:00 |
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Rose Thompson
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db3a7d5bbd
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More code cleanup for CacheSim.py
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2024-11-13 10:45:33 -06:00 |
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Jordan Carlin
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b58fda89bd
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Merge pull request #1088 from rosethompson/main
Fixes lint warnings in loggers.sv updates spi device tree for vcu108
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2024-11-13 08:39:32 -08:00 |
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Rose Thompson
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77d47e531f
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Merge branch 'main' into lrufixes
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2024-11-13 10:34:21 -06:00 |
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David Harris
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b6c69fa8a3
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Merge pull request #1089 from coreyqh/dev
Add ZicsrF coverage to fcov
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2024-11-13 03:02:01 -08:00 |
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David Harris
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585a1df8c2
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Merge pull request #1085 from Daniyal-R-A/Z_enable
Enabling Bit manipulation Instructions in coverage.svh files
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2024-11-13 03:01:43 -08:00 |
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Rose Thompson
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2fe73f8174
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Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore.
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2024-11-13 00:02:51 -06:00 |
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Rose Thompson
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8993432928
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Resolved issue with questa not liking the TEST +arg as a generate.
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2024-11-12 23:57:30 -06:00 |
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Corey Hickson
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dcaef2080b
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Add ZicsrF coverage to fcov
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2024-11-12 19:09:50 -08:00 |
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Rose Thompson
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ef7072b7c2
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Merge branch 'main' into lrufixes
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2024-11-12 17:57:28 -06:00 |
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Rose Thompson
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5346680758
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Final code cleanup.
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2024-11-12 17:52:16 -06:00 |
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Rose Thompson
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b8cafb5198
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More code cleanup.
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2024-11-12 17:51:22 -06:00 |
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