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Merge pull request #1100 from davidharrishmc/dev

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Fixed tracer warnings, removed fcovimp support
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Rose Thompson 2024-11-15 08:00:10 -06:00 committed by GitHub
commit fbd89eef83
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4 changed files with 8 additions and 40 deletions
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3
.gitignore vendored
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@ -105,9 +105,6 @@ sim/questa/wkdir
sim/questa/ucdb
sim/questa/cov
sim/questa/fcov
sim/questa/fcovrvvi
sim/questa/fcovrvvi_logs
sim/questa/fcovrvvi_ucdb
sim/questa/fcov_logs
sim/questa/fcov_ucdb
sim/questa/riscv.ucdb

13
bin/wsim
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@ -27,7 +27,6 @@ parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilat
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true")
parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
@ -70,7 +69,7 @@ if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite
exit(1)
# Validate arguments
if (args.gui or args.ccov or args.fcov or args.fcovimp or args.lockstep or args.lockstepverbose):
if (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose):
if args.sim not in ["questa", "vcs"]:
print("Option only supported for Questa and VCS")
exit(1)
@ -88,7 +87,7 @@ if (args.tb == "testbench_fp"):
if(int(args.locksteplog) >= 1): EnableLog = 1
else: EnableLog = 0
prefix = ""
if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp):
if (args.lockstep or args.lockstepverbose or args.fcov):
if (args.sim == "questa" or args.sim == "vcs"):
imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
@ -101,12 +100,6 @@ if (args.sim == "questa"):
if (args.lockstep or args.lockstepverbose):
if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
else: ImperasPlusArgs = ""
if(args.fcovimp):
CovEnableStr = "1" if int(args.covlog) > 0 else "0"
if(args.covlog >= 1): EnableLog = 1
else: EnableLog = 0
ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr
suffix = ""
if(args.fcov):
CovEnableStr = "1" if int(args.covlog) > 0 else "0";
if(args.covlog >= 1): EnableLog = 1
@ -130,8 +123,6 @@ if (args.ccov):
flags += " --ccov"
if (args.fcov):
flags += " --fcov"
if (args.fcovimp):
flags += " --fcovimp"
# create the output sub-directories.
regressionDir = WALLY + '/sim/'

20
sim/questa/wally.do
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@ -103,26 +103,6 @@ if {[lcheck lst "--ccov"]} {
set CoverageVsimArg "-coverage"
}
# if --fcovimp found set flag and remove from list
if {[lcheck lst "--fcovimp"]} {
set FunctCoverage 1
set FCvlog "+define+INCLUDE_TRACE2COV \
+define+IDV_INCLUDE_TRACE2COV \
+define+COVER_BASE_RV64I \
+define+COVER_LEVEL_DV_PR_EXT \
+incdir+${IMPERAS_HOME}/ImpProprietary/source/host/riscvISACOV/source"
set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
# Uncomment various cover statements below to control which extensions get functional coverage
lappend FCdefineCOVER_EXTS "+define+COVER_RV64I"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64M"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64A"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64F"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64D"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64ZICSR"
#lappend FCdefineCOVER_EXTS "+define+COVER_RV64C"
}
# if --fcov found set flag and remove from list
if {[lcheck lst "--fcov"]} {
set FunctCoverage 1

12
testbench/common/wallyTracer.sv
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@ -115,21 +115,21 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
logic valid;
int csrid;
always_comb begin
// Since we are detected the CSR change by comparing the old value we need to
// ensure the CSR is detected when the pipeline's Writeback stage is not
// stalled. If it is stalled we want CSRArray to hold the old value.
if(valid) begin
// PMPCFG CSRs (space is 0-15 3a0 - 3af)
int inc = P.XLEN == 32 ? 4 : 8;
localparam inc = P.XLEN == 32 ? 4 : 8;
int i, i4, i8, csrid;
logic [P.XLEN-1:0] pmp;
for (i=0; i<P.PMP_ENTRIES; i+=inc) begin
i4 = i / 4;
i8 = (i / inc) * inc;
csrid = 12'h3A0 + i4;
pmp = 0;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+0] << 0;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+1] << 8;
@ -140,15 +140,13 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+6] << 48;
pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56;
csrid = 12'h3A0 + i4;
CSRArray[csrid] = pmp;
end
// PMPADDR CSRs (space is 0-63 3b0 - 3ef)
for (i=0; i<P.PMP_ENTRIES; i++) begin
csrid = 12'h3B0 + i;;
pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
csrid = 12'h3B0 + i;
CSRArray[csrid] = pmp;
end
@ -219,6 +217,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
end
end else begin // hold the old value if the pipeline is stalled.
// PMP CFG 3A0 to 3AF
int csrid;
for(csrid='h3A0; csrid<='h3AF; csrid++)
CSRArray[csrid] = CSRArrayOld[csrid];
@ -382,6 +381,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
// record previous csr value.
integer index4;
always_ff @(posedge clk) begin
int csrid;
// PMP CFG 3A0 to 3AF
for(csrid='h3A0; csrid<='h3AF; csrid++)
CSRArrayOld[csrid] = CSRArray[csrid];