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Author SHA1 Message Date
Ross Thompson
1fec535b32 Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram. 
but the data is wrong.
 2023-04-19 10:35:18 -05:00
Ross Thompson
224bf74530 Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed. 2023-04-18 17:45:41 -05:00
Ross Thompson
367bd0f8dc More debug stuff. 2023-04-18 16:00:10 -05:00
Ross Thompson
668e69fdc9 Added more signals to debugger in hopes I can figure out why the mig is not responding. 2023-04-18 15:51:52 -05:00
Ross Thompson
3588c53e66 It's almost working. 2023-04-18 14:24:59 -05:00
Ross Thompson
deb0bfc24d Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. 2023-04-17 20:05:59 -05:00
Ross Thompson
777bec2e24 Fixed timing constraint issue. 2023-04-17 19:53:43 -05:00
Ross Thompson
b2b30936be Found the DDR3 memory is not ready when issuing the first store. 2023-04-17 19:33:13 -05:00
Ross Thompson
fbbba0e5c2 Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8. 2023-04-17 18:39:25 -05:00
Ross Thompson
2cbaa5c27b Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way. 2023-04-17 16:37:18 -05:00
Ross Thompson
480562e53e Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there. 2023-04-17 16:00:02 -05:00
Ross Thompson
b0f0fb1da7 Adding in the ILA to the arty a7. 2023-04-17 14:54:10 -05:00
Ross Thompson
30d017c258 Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster. 2023-04-17 12:16:31 -05:00
Ross Thompson
fe692dacce Finally got the arty a7 to build. 2023-04-17 11:54:22 -05:00
Ross Thompson
4ad33d7acc OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :( 2023-04-17 11:10:19 -05:00
Ross Thompson
5591b447d6 Fixed more issues with arty a7 constarints. 2023-04-16 13:25:02 -05:00
Ross Thompson
f4734c0d1b Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
 2023-04-15 11:13:28 -05:00
Ross Thompson
2f8359e6cc Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure. 2023-04-14 18:02:16 -05:00
Ross Thompson
d967e05c20 Finally fixed the ddr3 mig script to work correclty. 2023-04-14 11:41:51 -05:00
Ross Thompson
777edb0fcd Progress on arty a7 board. 2023-04-13 17:57:12 -05:00
Ross Thompson
4563b650bf Fixed more bugs in the ila debug constraints. 2023-04-11 14:32:53 -05:00
Ross Thompson
c1ac84c06b Merge branch 'main' of github.com:ross144/cvw 2023-04-11 14:31:08 -05:00
Ross Thompson
e490ab09cf Updated to help debut Jacob's crossbar woes. 2023-04-11 14:22:42 -05:00
Ross Thompson
6c07a2e595 Fixed sum bugs with arty a7 ila script. 2023-04-11 10:00:06 -05:00
Ross Thompson
c4e5b8db49 Updates for arty a7. 2023-04-10 17:02:19 -05:00
Ross Thompson
5bcb0f6ace Fixed syntax errors in arty7 top level. 2023-04-10 16:08:40 -05:00
Ross Thompson
0700202001 Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
Ross Thompson
9d9c2b170d Finally building ddr3 xilinx ip from script. 2023-04-10 14:36:33 -05:00
Ross Thompson
e7f494ef95 Started putting together the arty a7 board package files. 2023-04-10 13:15:55 -05:00
Ross Thompson
009a020c88 Updated wally figure again to increase resolution. 2023-04-09 12:26:15 -05:00
Ross Thompson
1534ae1879 Updated wally top level figure to fix issue 172. 2023-04-09 12:20:43 -05:00
Ross Thompson
81074a822a Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-09 12:19:44 -05:00
David Harris
c197739841 Merge pull request #222 from kjprime/main 
Remove unnecessary check from compressed instruction decode
 2023-04-09 04:56:21 -07:00
David Harris
df2943b9c1 Merge pull request #221 from dherreravicioso/main 
Added test coverage for Privilege Unit in CSRs
 2023-04-09 04:54:36 -07:00
Kevin Thomas
f7838b869b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
Diego Herrera Vicioso
5f9c443781 Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs. 2023-04-08 16:40:36 -07:00
Ross Thompson
ba08c39eef Merge pull request #220 from davidharrishmc/dev 
Obscure coverage fixes
 2023-04-08 10:27:31 -05:00
David Harris
1c47221983 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-07 21:57:18 -07:00
David Harris
7affe2bdca Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00
David Harris
2f4074b9c2 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
Ross Thompson
cfab7c8b45 Merge pull request #219 from davidharrishmc/dev 
Spill logic coverage and fdivsqrt cleanup
 2023-04-07 23:30:52 -05:00
David Harris
5cdd3d57c7 Commented WFI non-flush in writeback stage of hazard unit 2023-04-07 21:27:13 -07:00
David Harris
b27199e276 Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
David Harris
0d2de13990 Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf 2023-04-07 21:11:01 -07:00
David Harris
bf9db11a57 Fixed priv.S to initialize stimecmp and agree with ImperasDV 2023-04-07 20:44:01 -07:00
David Harris
9394389fec Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
David Harris
16eca598ba Fixed WALLY-init-lib to return correctly even from traps from compressed instructions 2023-04-07 20:24:33 -07:00
David Harris
a49f1f785e Fixed enabling machine timer interrupt 2023-04-06 22:18:33 -07:00
David Harris
8ef9891e46 vm64 tests 2023-04-06 21:42:47 -07:00
David Harris
19c39628fa Division cleanup 2023-04-06 21:42:34 -07:00