David Harris
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1bac0de954
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Reparitioned sign logic in fdivsqrt to match paper
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2023-11-06 14:11:42 -08:00 |
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David Harris
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fac0c1b125
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Fixed bit manpulation on imperas config
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2023-11-06 14:11:01 -08:00 |
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David Harris
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dd3f05b86e
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Shortened path to PCSrcE in logger to avoid problematic hierarchical reference
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2023-11-05 07:06:53 -08:00 |
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David Harris
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2688a34370
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Fixed Svnapot_page_mask for imperas.ic
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2023-11-05 06:51:01 -08:00 |
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David Harris
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2c38692a03
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Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue
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2023-11-04 20:36:05 -07:00 |
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David Harris
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3f4bf4a010
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Verilator improvements
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2023-11-04 03:21:07 -07:00 |
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David Harris
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45e5e694ec
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-03 16:04:10 -07:00 |
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David Harris
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4ff4e66c0c
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Merge pull request #454 from naichewa/spi
add SPI to cvw/main
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2023-11-03 16:02:57 -07:00 |
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naichewa
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96c0b04238
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merge main, pull /A/ tests
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2023-11-03 13:16:19 -07:00 |
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naichewa
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75658d5f8b
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Merge branch 'main' into spi
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2023-11-03 13:15:15 -07:00 |
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David Harris
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5e84d5e613
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set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t
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2023-11-03 06:37:05 -07:00 |
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David Harris
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31adea3db0
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Modified rams to take USE_SRAM rather than P to facilitate synthesis
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2023-11-03 05:44:13 -07:00 |
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David Harris
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0b35c2ea56
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Updated testbenches to capture InstrM because it may be optimized out of IFU
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2023-11-03 05:24:15 -07:00 |
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David Harris
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9b7f385c50
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Temporary fix of InstrM to prevent testbench hanging
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2023-11-03 04:59:44 -07:00 |
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David Harris
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409ecc53bd
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Fixed regression error of watchdog timeout when PCM is optimized out of the IFU
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2023-11-03 04:38:27 -07:00 |
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naichewa
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6a148349de
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added test cases
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2023-11-02 15:43:08 -07:00 |
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naichewa
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08cf75783e
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added test cases
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2023-11-02 15:42:28 -07:00 |
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Rose Thompson
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92d4d7626c
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Merge pull request #449 from davidharrishmc/dev
Synthesis cleanup
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2023-11-02 12:26:55 -05:00 |
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David Harris
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c99d29cf95
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Removed .gitattributes
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2023-11-01 17:50:44 -07:00 |
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naichewa
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b59abc2dcc
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correct exclusion tags and reset testbench
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2023-11-01 10:34:39 -07:00 |
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naichewa
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8027a71e86
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harris code review 3
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2023-11-01 10:14:15 -07:00 |
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David Harris
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c639f92d27
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Improved comments about memory read paths
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2023-11-01 07:00:17 -07:00 |
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naichewa
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755c055f74
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comments, more test cases
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2023-11-01 01:26:34 -07:00 |
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naichewa
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792ddec064
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code review harris
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2023-10-31 12:27:41 -07:00 |
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David Harris
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6f021aac54
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Fixes to config extraction
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2023-10-31 06:27:55 -07:00 |
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David Harris
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bd6e189680
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130 nm synthesis script improvements
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2023-10-30 20:57:35 -07:00 |
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David Harris
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d2ccba9a49
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Conditionally instantiate hardware in ifu
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2023-10-30 20:55:00 -07:00 |
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David Harris
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d0735887de
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Gated InstrOrigM and PCMReg when not needed
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2023-10-30 20:05:37 -07:00 |
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David Harris
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4bd830e578
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rom1p1r code cleanup
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2023-10-30 19:47:49 -07:00 |
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David Harris
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7b3dcdc262
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rom1p1r code cleanup
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2023-10-30 19:46:38 -07:00 |
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David Harris
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c472f4dc3c
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Made 2-bit AdrReg conditional on being needed
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2023-10-30 19:13:43 -07:00 |
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naichewa
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3570468ef5
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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7a0fb9a193
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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Rose Thompson
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e3f769a563
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Merge pull request #445 from davidharrishmc/dev
Fix issue 444; no delegating misaligned instructions if they can't happen
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2023-10-30 12:25:42 -05:00 |
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David Harris
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4d191e63cc
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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David Harris
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12d1aed8a9
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Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.
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2023-10-30 07:06:34 -07:00 |
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Rose Thompson
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77e6ac487a
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Merge pull request #443 from davidharrishmc/dev
Wrapper synthesis fix.
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2023-10-27 09:25:06 -05:00 |
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David Harris
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5ca5443835
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Fixed reporting of timing on modules with wrappers
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2023-10-26 20:14:14 -07:00 |
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David Harris
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d5d196b870
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-10-26 19:02:05 -07:00 |
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David Harris
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b1796daca7
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Merge pull request #441 from ross144/main
Fixed issues #200
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2023-10-26 10:26:58 -07:00 |
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Rose Thompson
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9ca3bfc2c8
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Updated comments about Interrupt and wfi.
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2023-10-26 12:24:36 -05:00 |
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Rose Thompson
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63bcc7655c
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Forgot to include this file in the last commit.
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2023-10-26 12:20:42 -05:00 |
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Rose Thompson
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4c4103dfe8
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-10-26 12:15:22 -05:00 |
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Rose Thompson
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dd9059317f
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Cleaned up the implementation changes for wfi.
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2023-10-24 23:11:48 -05:00 |
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Rose Thompson
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e4aebbaaa5
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This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps.
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2023-10-24 22:58:26 -05:00 |
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Rose Thompson
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bc877e9ca7
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Possible fix for wfi.
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2023-10-24 18:08:33 -05:00 |
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David Harris
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17fd0c90da
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Fixed warnings of signed conversion and for Design Compiler
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2023-10-24 14:01:43 -07:00 |
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David Harris
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7fc5268f47
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Tested assembly language file for the pause example
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2023-10-24 10:45:41 -07:00 |
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David Harris
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de52710a60
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Merge pull request #439 from ross144/main
Fixes to branch predictor processing scripts.
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2023-10-24 08:31:06 -07:00 |
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Rose Thompson
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25a3a2f33b
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Fixed bug in bpred-sim.py for btb and class size sweep.
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2023-10-24 10:29:02 -05:00 |
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