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Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue

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This commit is contained in:
David Harris 2023-11-04 20:36:05 -07:00
parent 3f4bf4a010
commit 2c38692a03
5 changed files with 25 additions and 24 deletions
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4
testbench/testbench-fp.sv
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@ -644,11 +644,11 @@ module testbenchfp;
// Read the first test
initial begin
//string testname = {`PATH, Tests[TestNum]};
string p = `PATH;
static string pp = `PATH;
string testname;
string tt0;
tt0 = $psprintf("%s", Tests[TestNum]);
testname = {p, tt0};
testname = {pp, tt0};
$display("Here you are %s", testname);
$display("\n\nRunning %s vectors ", Tests[TestNum]);
$readmemh(testname, TestVectors);

7
testbench/testbench-imperas.sv
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@ -72,6 +72,7 @@ module testbench;
logic HMASTLOCK;
logic HCLK, HRESETn;
logic [P.XLEN-1:0] PCW;
logic [31:0] NextInstrE, InstrM;
string ProgramAddrMapFile, ProgramLabelMapFile;
integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
@ -81,7 +82,8 @@ module testbench;
logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
logic UARTSin, UARTSout;
logic SPIIn, SPIOut;
logic [3:0] SPICS;
logic SDCIntr;
logic HREADY;
@ -255,7 +257,7 @@ module testbench;
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIntr);
.UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn);
// Track names of instructions
instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
@ -299,7 +301,6 @@ module testbench;
end
// Duplicate copy of pipeline registers that are optimized out of some configurations
logic [31:0] NextInstrE, InstrM;
mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE);
flopenr #(32) InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM);

15
testbench/testbench-linux-imperas.sv
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@ -282,7 +282,9 @@ module testbench;
logic SDCCmdOE;
logic [3:0] SDCDatIn;
logic SDCIntr;
logic SPIIn, SPIOut;
logic [3:0] SPICS;
// Hardwire UART, GPIO pins
assign GPIOIN = 0;
@ -440,13 +442,10 @@ module testbench;
// Wally
wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext,
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK,
.TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout,
.SDCIntr);
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn);
// W-stage hardware not needed by Wally itself
parameter nop = 'h13;

13
testbench/testbench-linux.sv
View File

@ -258,6 +258,8 @@ module testbench;
logic [31:0] GPIOIN;
logic [31:0] GPIOOUT, GPIOEN;
logic UARTSin, UARTSout;
logic SPIIn, SPIOut;
logic [3:0] SPICS;
// FPGA-specific Stuff
logic SDCIntr;
@ -268,13 +270,10 @@ module testbench;
assign SDCIntr = 0;
// Wally
wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext,
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HSELEXTSDC, .HRESPEXT, .HCLK,
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK,
.TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout,
.SDCIntr);
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn);
// W-stage hardware not needed by Wally itself
parameter nop = 'h13;

10
testbench/testbench-xcelium.sv
View File

@ -70,6 +70,8 @@ module testbench;
logic [3:0] SDCDatIn;
tri1 [3:0] SDCDat;
tri1 SDCCmd;
logic SPIIn, SPIOut;
logic [3:0] SPICS;
logic HREADY;
logic HSELEXT;
@ -426,10 +428,10 @@ module testbench;
assign SDCDat = '0;
end
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn);
// generate clock to sequence tests
always begin