Rose Thompson
bad9afc012
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-10-23 16:14:30 -05:00
Rose Thompson
c296bd3a02
Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction.
2023-10-23 16:09:40 -05:00
Rose Thompson
bce15ce367
Added support for branch counters when there is no branch predictor.
2023-10-23 15:32:03 -05:00
Rose Thompson
2b031ea445
Fixed issue 250. instruction classification was not correct for jalr ra (non zero).
2023-10-23 15:30:43 -05:00
Rose Thompson
7347ed2527
Addeed script to sweep sim_bp for btb.
2023-10-23 15:29:50 -05:00
David Harris
deebc84084
Merge pull request #438 from ross144/main
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Fixed comments in cboz and cbom tests.
2023-10-20 17:15:59 -07:00
Rose Thompson
e3154bb7a3
Updated comments in the cboz tests.
2023-10-20 15:15:47 -05:00
Rose Thompson
74574f96cf
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-10-20 15:14:02 -05:00
Rose Thompson
badfc1e4bb
Updated comments for the cbom tests.
2023-10-20 15:13:52 -05:00
Rose Thompson
99671ebbcd
Merge pull request #437 from davidharrishmc/dev
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synth improvements
2023-10-19 16:23:34 -05:00
David Harris
46d16305a4
Set drive for Sky130
2023-10-19 13:46:30 -07:00
David Harris
aa3bc10259
Modified log2 coding to avoid synthesis warning
2023-10-19 11:16:02 -07:00
Rose Thompson
c5de241436
Merge pull request #436 from davidharrishmc/dev
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Automatic generation of synthesis wrappers when needed
2023-10-19 12:51:24 -05:00
David Harris
b28777fae0
Removed wrapper from wallySynth because it is automatic now
2023-10-19 10:49:06 -07:00
David Harris
8c6b17de6d
Updated wrapper generation to be automatic without specifying WRAPPER=1; instead looks for cvw_t in the file. Also starting to add OSU 130 nm synthesis.
2023-10-19 10:44:03 -07:00
David Harris
379337fee0
Adjusted synthesis scripts to report on DESIGN even when a wrapper is used
2023-10-19 06:16:52 -07:00
Rose Thompson
ba6785d04f
Merge pull request #434 from davidharrishmc/dev
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Config and peripheral cleanup
2023-10-18 17:58:29 -05:00
David Harris
054d9ed38c
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-10-18 14:40:19 -07:00
David Harris
46b1ff00d6
Merge pull request #435 from kipmacsaigoren/synth_wrapper_gen
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synth wrapper generation bug fix
2023-10-18 14:34:37 -07:00
Kevin Kim
0a15466f21
wrapper bug fix
2023-10-18 14:29:46 -07:00
David Harris
09b3a49471
Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates
2023-10-18 05:50:41 -07:00
David Harris
b01e1604e0
Config file cleanup
2023-10-18 05:38:36 -07:00
David Harris
f663b26e14
Merge pull request #433 from ross144/main
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Reverted linux testbench to not check for match against QEMU.
2023-10-17 11:13:11 -07:00
Rose Thompson
b3a248cc5b
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-10-17 10:01:35 -05:00
Rose Thompson
55c1560467
Reverted linux testbench to not check for match against QEMU.
2023-10-17 10:00:50 -05:00
naichewa
19e45a9182
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
naichewa
95daef38d1
sync fifo passes
2023-10-16 22:57:02 -07:00
Rose Thompson
dd7f7b5c6e
Merge pull request #431 from davidharrishmc/dev
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Dev
2023-10-16 17:36:31 -05:00
David Harris
8dd1617409
Merged testbench
2023-10-16 13:52:24 -07:00
David Harris
b39ba7b4f8
Renamed wally-config to config in many comments
2023-10-16 13:49:09 -07:00
David Harris
1e2f1089ca
Incorporated new AMO tests from riscv-arch-test
2023-10-16 10:25:45 -07:00
David Harris
5f9b555b93
Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
2023-10-15 15:31:03 -07:00
David Harris
88745f9265
Added WALLY minfo test for rv32
2023-10-15 06:48:22 -07:00
David Harris
b8a17afd5d
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
David Harris
cc14c0a858
Merge pull request #429 from ross144/main
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renamed imperas testbench to testbench-imperas.sv, fixed SDC timing bug
2023-10-13 15:32:43 -07:00
naichewa
59afc3b92c
always working after reg bit swizzle changes
2023-10-13 14:22:32 -07:00
Rose Thompson
0a06effdca
Added missing files.
2023-10-13 15:10:58 -05:00
Rose Thompson
045b0adbbd
Renamed testbench_imperas.sv to testbench-imperas.sv
2023-10-13 14:56:45 -05:00
Rose Thompson
63d6b1d1c8
Removed P.FPGA from testbench.
2023-10-13 14:08:17 -05:00
Ross Thompson
7ec323346e
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-10-13 13:44:19 -05:00
Ross Thompson
31a2d73375
Merge branch 'main' of github.com:ross144/cvw
2023-10-13 12:30:52 -05:00
Ross Thompson
4884f3d527
Change to flash-sd.sh to fix relative path to device tree.
2023-10-13 12:30:21 -05:00
naichewa
dd3e701447
correct delay0, fmt register test entries
2023-10-12 15:13:23 -07:00
naichewa
1fa4ad90ec
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
Ross Thompson
3d917f29d3
Fixed bug with flash script.
2023-10-10 18:05:35 -05:00
Ross Thompson
8cc6657644
Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.
2023-10-10 17:46:12 -05:00
David Harris
2f6e39defc
Merge pull request #424 from ross144/main
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Fixed issue #412 The root cause was DTLB miss leads to page fault exception with concurrent I$ miss. The HPTW hits all entries in the D$ and quickly faults. However the I$ is still waiting on the main memory. The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.
2023-10-10 07:09:15 -07:00
Ross Thompson
9e149b77f7
Merge branch 'main' of github.com:ross144/cvw
2023-10-09 16:08:07 -05:00
Ross Thompson
4a61d1b4f1
Fixed issue #412
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The root cause was DTLB miss leads to page fault exception with concurrent I$ miss. The HPTW hits all entries in the D$ and quickly faults. However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.
The simplest solution is to use CommittedF to delay Exceptions like with Interrupts. Note this cannot happen with CommittedM. If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
2023-10-09 16:03:37 -05:00
Rose Thompson
c6ecc15d51
Merge pull request #422 from eroom1966/main
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Update to IDV
2023-10-06 07:51:14 -05:00
