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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
comments, more test cases
This commit is contained in:
naichewa
parent
792ddec064
commit
755c055f74
@ -27,23 +27,16 @@
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// Current limitations: Flash read sequencer mode not implemented, dual and quad modes untestable with current test plan.
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// Hardware interlock change to busy signal
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// relook at fifo empty full logic; might be that watermark level is low when full
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// ChipSelectInternal boolean logic simplification (Harris suggestion)
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// document timing on loopback testing
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// change SCLKenable comparison to equals if possible
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// Explain how sck divider gets to correct value
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// HoldModeDeassert verilater lint
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// Comment on FIFOs: readenable, watermark calculations
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// write tests for fifo full and empty watermark edge cases
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// HoldModeDeassert verilater lint, relook in general
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// Comment on FIFOs: watermark calculations
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/* high level explanation of architecture
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SPI module is written to the specifications described in FU540-C000-v1.0. At the top level, it is consists of synchronous 8 byte transmit and recieve FIFOs connected to shift registers.
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The FIFOs are connected to WALLY by an apb bus control register interface, which includes various control registers for modifying the SPI transmission along with registers for writing
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to the transmit FIFO and reading from the receive FIFO. The transmissions themselves are then controlled by a finite state machine. The SPI module uses 4 tristate pins for SPI input/output,
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along with a 4 bit Chip Select signal, a clock signal, and an interrupt signal to WALLY.
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*/
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module spi_apb import cvw::*; #(parameter cvw_t P) (
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input logic PCLK, PRESETn,
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input logic PSEL,
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@ -63,24 +56,23 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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//SPI registers
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logic [11:0] SckDiv, HISckDiv;
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logic [1:0] SckMode, HISckMode;
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logic [1:0] ChipSelectID, HIChipSelectID;
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logic [3:0] ChipSelectDef, HIChipSelectDef;
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logic [1:0] ChipSelectMode, HIChipSelectMode;
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logic [15:0] Delay0, Delay1, HIDelay0, HIDelay1;
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logic [7:0] Format, HIFormat;
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logic [11:0] SckDiv;
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logic [1:0] SckMode;
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logic [1:0] ChipSelectID;
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logic [3:0] ChipSelectDef;
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logic [1:0] ChipSelectMode;
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logic [15:0] Delay0, Delay1;
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logic [7:0] Format;
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logic [8:0] ReceiveData;
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logic [8:0] ReceiveDataPlaceholder;
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logic [2:0] TransmitWatermark, ReceiveWatermark, HITransmitWatermark, HIReceiveWatermark;
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logic [2:0] TransmitWatermark, ReceiveWatermark;
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logic [8:0] TransmitData;
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logic [1:0] InterruptEnable, InterruptPending, HIInterruptEnable;
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logic [1:0] InterruptEnable, InterruptPending;
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//bus interface signals
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logic [7:0] Entry;
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logic Memwrite;
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logic [31:0] Din, Dout;
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logic busy;
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//FIFO FSM signals
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logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
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@ -151,12 +143,14 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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logic ReceiveShiftFullDelayPCLK;
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logic [2:0] LeftShiftAmount;
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logic [7:0] ASR; // AlignedReceiveShiftReg
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logic DelayMode;
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// apb
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assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign Memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
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assign PREADY = 1'b1; // tie high if hardware interlock solution doesn't involve bus
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//assign PREADY = TransmitInactive; // tie PREADY to transmission for hardware interlock
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//assign PREADY = 1'b1; // tie high if hardware interlock solution doesn't involve bus
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assign PREADY = TransmitInactive; // tie PREADY to transmission for hardware interlock
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@ -189,17 +183,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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ReceiveWatermark <= #1 3'b0;
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InterruptEnable <= #1 2'b0;
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InterruptPending <= #1 2'b0;
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HISckDiv <= #1 12'd3;
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HISckMode <= #1 2'b0;
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HIChipSelectID <= #1 2'b0;
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HIChipSelectDef <= #1 4'b1111;
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HIChipSelectMode <= #1 0;
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HIDelay0 <= #1 {8'b1,8'b1};
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HIDelay1 <= #1 {8'b0,8'b1};
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HIFormat <= #1 {8'b10000000};
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HITransmitWatermark <= #1 3'b0;
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HIReceiveWatermark <= #1 3'b0;
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HIInterruptEnable <= #1 2'b0;
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end else begin //writes
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//According to FU540 spec: Once interrupt is pending, it will remain set until number
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//of entries in tx/rx fifo is strictly more/less than tx/rxmark
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@ -209,32 +192,19 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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/* verilator lint_off CASEINCOMPLETE */
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if (Memwrite)
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case(Entry) //flop to sample inputs
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8'h00: HISckDiv <= Din[11:0];
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8'h04: HISckMode <= Din[1:0];
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8'h10: HIChipSelectID <= Din[1:0];
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8'h14: HIChipSelectDef <= Din[3:0];
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8'h18: HIChipSelectMode <= Din[1:0];
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8'h28: HIDelay0 <= {Din[23:16], Din[7:0]};
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8'h2C: HIDelay1 <= {Din[23:16], Din[7:0]};
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8'h40: HIFormat <= {Din[19:16], Din[3:0]};
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8'h00: SckDiv <= Din[11:0];
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8'h04: SckMode <= Din[1:0];
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8'h10: ChipSelectID <= Din[1:0];
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8'h14: ChipSelectDef <= Din[3:0];
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8'h18: ChipSelectMode <= Din[1:0];
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8'h28: Delay0 <= {Din[23:16], Din[7:0]};
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8'h2C: Delay1 <= {Din[23:16], Din[7:0]};
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8'h40: Format <= {Din[19:16], Din[3:0]};
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8'h48: if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0];
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8'h50: HITransmitWatermark <= Din[2:0];
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8'h54: HIReceiveWatermark <= Din[2:0];
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8'h70: HIInterruptEnable <= Din[1:0];
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8'h50: TransmitWatermark <= Din[2:0];
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8'h54: ReceiveWatermark <= Din[2:0];
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8'h70: InterruptEnable <= Din[1:0];
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endcase
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if (TransmitInactive) begin
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SckDiv <= HISckDiv;
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SckMode <= HISckMode;
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ChipSelectID <= HIChipSelectID;
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ChipSelectDef <= HIChipSelectDef;
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ChipSelectMode <= HIChipSelectMode;
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Delay0 <= HIDelay0;
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Delay1 <= HIDelay1;
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Format <= HIFormat;
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TransmitWatermark <= HITransmitWatermark;
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ReceiveWatermark <= HIReceiveWatermark;
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InterruptEnable <= HIInterruptEnable;
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end
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/* verilator lint_off CASEINCOMPLETE */
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//interrupt clearance
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InterruptPending[0] <= TransmitReadMark;
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@ -260,10 +230,10 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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assign SCLKenable = (DivCounter >= {1'b0,SckDiv});
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assign SCLKenableEarly = ((DivCounter + 13'b1) >= {1'b0, SckDiv});
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//
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// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
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// generates a high signal at the rising and falling edge of SCLK by counting from 0 to SckDiv
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assign SCLKenable = (DivCounter == {1'b0,SckDiv});
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assign SCLKenableEarly = ((DivCounter + 13'b1) == {1'b0, SckDiv});
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) DivCounter <= #1 0;
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else if (SCLKenable) DivCounter <= 0;
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@ -274,10 +244,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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if (~PRESETn) SCLKenableDelay <= 0;
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else SCLKenableDelay <= SCLKenable;
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//SCK_CONTROL
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//Boolean logic that tracks frame progression
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//multiplies frame count by 2 or 4 if in dual or quad mode
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always_comb
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case(Format[1:0])
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2'b00: FrameCountShifted = FrameCount;
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@ -287,7 +255,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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endcase
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//Calculates penultimate frame
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//Frame compare doubles number of frames in dual or qyad mode to account for half-duplex communication
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//Frame compare doubles number of frames in dual or quad mode to account for half-duplex communication
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//FrameCompareProtocol further adjusts comparison according to dual or quad mode
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always_comb
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@ -316,7 +284,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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endcase
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//Signals that track frame count comparisons
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assign FrameCompareBoolean = (FrameCountShifted < FrameCompareProtocol);
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assign ReceivePenultimateFrameCount = FrameCountShifted + ReceivePenultimateFrame;
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@ -324,8 +291,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// Computing delays
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// When sckmode.pha = 0, an extra half-period delay is implicit in the cs-sck delay, and vice-versa for sck-cs
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assign Delay0Compare = SckMode[0] ? (Delay0Count >= ({Delay0[7:0], 1'b0})) : (Delay0Count >= ({Delay0[7:0], 1'b0} + 9'b1));
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assign Delay1Compare = SckMode[0] ? (Delay1Count >= (({Delay0[15:8], 1'b0}) + 9'b1)) : (Delay1Count >= ({Delay0[15:8], 1'b0}));
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assign InterCSCompare = (InterCSCount >= ({Delay1[7:0],1'b0}));
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@ -336,7 +301,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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assign FrameCompare = (Format[0] | Format[1]) ? ({Format[7:4], 1'b0}) : {1'b0,Format[7:4]};
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// Transmit and Receive FIFOs
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//calculate when tx/rx shift registers are full/empty
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TransmitShiftFSM TransmitShiftFSM_1 (PCLK, PRESETn, TransmitFIFOReadEmpty, ReceivePenultimateFrameBoolean, Active0, TransmitShiftEmpty);
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ReceiveShiftFSM ReceiveShiftFSM_1 (PCLK, PRESETn, SCLKenable, ReceivePenultimateFrameBoolean, SampleEdge, SckMode[0], ReceiveShiftFull);
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@ -356,10 +320,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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else if (~ReceiveFIFOReadIncrement) ReceiveFIFOReadIncrement <= ((Entry == 8'h4C) & ~ReceiveFIFOReadEmpty & PSEL);
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else ReceiveFIFOReadIncrement <= 0;
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assign TransmitDataEndian = Format[2] ? {TransmitData[0], TransmitData[1], TransmitData[2], TransmitData[3], TransmitData[4], TransmitData[5], TransmitData[6], TransmitData[7]} : TransmitData[7:0];
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TransmitSynchFIFO #(3,8) txFIFO(PCLK, SCLKenable, PRESETn, TransmitFIFOWriteIncrementDelay, TransmitFIFOReadIncrement, TransmitDataEndian, TransmitWriteWatermarkLevel, TransmitWatermark[2:0], TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
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TransmitSynchFIFO #(3,8) txFIFO(PCLK, SCLKenable, PRESETn, TransmitFIFOWriteIncrementDelay, TransmitFIFOReadIncrement, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0], TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
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ReceiveSynchFIFO #(3,8) rxFIFO(PCLK, SCLKenable, PRESETn, ReceiveFIFOWriteIncrement, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel, ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark);
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always_ff @(posedge PCLK, negedge PRESETn)
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@ -377,7 +338,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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assign TransmitShiftRegLoad = ~TransmitShiftEmpty & ~Active | (((ChipSelectMode == 2'b10) & ~|(Delay1[15:8])) & ((ReceiveShiftFullDelay | ReceiveShiftFull) & ~SampleEdge & ~TransmitFIFOReadEmpty));
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//Main FSM which controls SPI transmission
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typedef enum logic [2:0] {CS_INACTIVE, DELAY_0, ACTIVE_0, ACTIVE_1, DELAY_1,INTER_CS, INTER_XFR} statetype;
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statetype state;
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@ -443,10 +403,9 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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/* verilator lint_off CASEINCOMPLETE */
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assign ChipSelectInternal = SckMode[0] ? ((state == CS_INACTIVE | state == INTER_CS | (state == DELAY_1 & ~|(Delay0[15:8]))) ? ChipSelectDef : ~ChipSelectDef) : ((state == CS_INACTIVE | state == INTER_CS | (state == ACTIVE_1 & ~|(Delay0[15:8]) & ReceiveShiftFull)) ? ChipSelectDef : ~ChipSelectDef);
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assign DelayMode = SckMode[0] ? (state == DELAY_1) : (state == ACTIVE_1 & ReceiveShiftFull);
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assign ChipSelectInternal = (state == CS_INACTIVE | state == INTER_CS | DelayMode & ~|(Delay0[15:8])) ? ChipSelectDef : ~ChipSelectDef;
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assign sck = (state == ACTIVE_0) ? ~SckMode[1] : SckMode[1];
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assign busy = (state == DELAY_0 | state == ACTIVE_0 | ((state == ACTIVE_1) & ~((|(Delay1[15:8]) & (ChipSelectMode[1:0]) == 2'b10) & ((FrameCount << Format[1:0]) >= FrameCompare))) | state == DELAY_1);
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assign Active = (state == ACTIVE_0 | state == ACTIVE_1);
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assign SampleEdge = SckMode[0] ? (state == ACTIVE_1) : (state == ACTIVE_0);
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assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4])));
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@ -454,6 +413,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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assign Active0 = (state == ACTIVE_0);
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assign Inactive = (state == CS_INACTIVE);
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// Ensures that when ChipSelectMode = hold, CS pin is deasserted only when a different value is written to csmode or csid or a write to csdeg changes the state
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// of the selected pin
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) HoldModeDeassert <= 0;
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else if (Inactive) HoldModeDeassert <= 0;
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@ -463,7 +424,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// Signal tracks which edge of sck to shift data
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always_comb
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case(SckMode[1:0])
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2'b00: sckPhaseSelect = ~sck & SCLKenable;
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@ -473,12 +434,13 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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default: sckPhaseSelect = sck & SCLKenable;
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endcase
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//Transmit shift register
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assign TransmitDataEndian = Format[2] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0];
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always_ff @(posedge PCLK, negedge PRESETn)
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if(~PRESETn) begin
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TransmitShiftReg <= 8'b0;
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end
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else if (TransmitShiftRegLoad) TransmitShiftReg <= TransmitFIFOReadData;
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else if (TransmitShiftRegLoad) TransmitShiftReg <= TransmitDataEndian;
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else if (sckPhaseSelect) begin
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//if ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty) & TransmitShiftEmpty) TransmitShiftReg <= TransmitFIFOReadData;
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if (Active) begin
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@ -492,7 +454,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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end
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always_comb
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//Transmit shift register
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//Output pin control based on single, dual, or quad mode
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if (Active | Delay0Compare | ~TransmitShiftEmpty) begin
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case(Format[1:0])
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2'b00: SPIOut = {3'b0,TransmitShiftReg[7]};
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@ -503,6 +465,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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endcase
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end else SPIOut = 4'b0;
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//If in loopback mode, receive shift register is connected directly to module's output pins. Else, connected to SPIIn
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//There are no setup/hold time issues because transmit shift register and receive shift register always shift/sample on opposite edges
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assign shiftin = P.SPI_LOOPBACK_TEST ? SPIOut : SPIIn;
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// Receive shift register
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@ -540,9 +504,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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endmodule
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module TransmitSynchFIFO #(parameter M =3 , N= 8)(
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input logic PCLK, ren, PRESETn,
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input logic PCLK, sclken, PRESETn,
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input logic winc,rinc,
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input logic [N-1:0] wdata,
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input logic [M-1:0] wwatermarklevel, rwatermarklevel,
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@ -562,41 +525,43 @@ module TransmitSynchFIFO #(parameter M =3 , N= 8)(
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always_ff @(posedge PCLK)
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if (winc & ~wfull) mem[waddr] <= wdata;
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// read flops are only enabled on sclk edges b/c transmit fifo is read on sclk
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) rptr <= 0;
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else if (ren) rptr <= rptrnext;
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if (~PRESETn) begin
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rptr <= 0;
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wptr <= 0;
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wfull <= 1'b0;
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rempty <= 1'b1;
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end
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else begin
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wfull <= wfull_val;
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wptr <= wptrnext;
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if (sclken) begin
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rptr <= rptrnext;
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rempty <= rempty_val;
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end
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end
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assign raddr = rptr[M-1:0];
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assign rptrnext = rptr + {3'b0, (rinc & ~rempty)};
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) wptr <= 0;
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else wptr <= wptrnext;
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assign rempty_val = (wptr == rptrnext);
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assign rwatermark = ((rptr[M-1:0] - wptr[M-1:0]) < rwatermarklevel);
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assign waddr = wptr[M-1:0];
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assign wwatermark = ((wptr[M-1:0] - rptr[M-1:0]) > wwatermarklevel);
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assign wptrnext = wptr + {3'b0, (winc & ~wfull)};
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assign rempty_val = (wptr == rptrnext);
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assign wfull_val = ({~wptrnext[M], wptrnext[M-1:0]} == rptr);
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assign rwatermark = ((rptr[M-1:0] - wptr[M-1:0]) < rwatermarklevel);
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) wfull <= 1'b0;
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else wfull <= wfull_val;
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) rempty <= 1'b1;
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||||
else if (ren) rempty <= rempty_val;
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||||
|
||||
|
||||
|
||||
endmodule
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||||
|
||||
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module ReceiveSynchFIFO #(parameter M =3 , N= 8)(
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||||
input logic PCLK, ren, PRESETn,
|
||||
input logic PCLK, sclken, PRESETn,
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||||
input logic winc,rinc,
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||||
input logic [N-1:0] wdata,
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||||
input logic [M-1:0] wwatermarklevel, rwatermarklevel,
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||||
@ -615,31 +580,34 @@ module ReceiveSynchFIFO #(parameter M =3 , N= 8)(
|
||||
assign rdata = mem[raddr];
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||||
always_ff @(posedge PCLK)
|
||||
if(winc & ~wfull & PCLK) mem[waddr] <= wdata;
|
||||
|
||||
//write flops are enabled only on sclk edges b/c receive fifo is written then
|
||||
always_ff @(posedge PCLK, negedge PRESETn)
|
||||
if (~PRESETn) rptr <= 0;
|
||||
else rptr <= rptrnext;
|
||||
if (~PRESETn) begin
|
||||
rptr <= 0;
|
||||
wptr <= 0;
|
||||
wfull <= 0;
|
||||
rempty <= 0;
|
||||
end else begin
|
||||
rptr <= rptrnext;
|
||||
rempty <= rempty_val;
|
||||
if (sclken) begin
|
||||
wptr <= wptrnext;
|
||||
wfull <= wfull_val;
|
||||
end
|
||||
end
|
||||
|
||||
assign rwatermark = ((rptr[M-1:0] - wptr[M-1:0]) < rwatermarklevel);
|
||||
assign raddr = rptr[M-1:0];
|
||||
assign rptrnext = rptr + {3'b0, (rinc & ~rempty)};
|
||||
assign rempty_val = (wptr == rptrnext);
|
||||
|
||||
always_ff @(posedge PCLK, negedge PRESETn)
|
||||
if (~PRESETn) rempty <= 1'b1;
|
||||
else rempty <= rempty_val;
|
||||
|
||||
always_ff @(posedge PCLK, negedge PRESETn)
|
||||
if (~PRESETn) wptr <= 0;
|
||||
else if (ren) wptr <= wptrnext;
|
||||
|
||||
assign waddr = wptr[M-1:0];
|
||||
assign wwatermark = ((wptr[M-1:0] - rptr[M-1:0]) > wwatermarklevel);
|
||||
assign wptrnext = wptr + {3'b0, (winc & ~wfull)};
|
||||
|
||||
assign wfull_val = ({~wptrnext[M], wptrnext[M-1:0]} == rptr);
|
||||
|
||||
always_ff @(posedge PCLK, negedge PRESETn)
|
||||
if (~PRESETn) wfull <= 1'b0;
|
||||
else if (ren) wfull <= wfull_val;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -306,12 +306,26 @@ test_cases:
|
||||
.8byte rx_data, 0x000000BC, read32_test
|
||||
.8byte rx_data, 0x000000AB, read32_test
|
||||
|
||||
# Test hold mode deassert conditions
|
||||
|
||||
.8byte delay1, 0x00000001, write32_test # reset delay1 register
|
||||
.8byte delay0, 0x00010001, write32_test # reset delay0 register
|
||||
.8byte cs_mode, 0x00000002, write32_test # set cs_mode to hold
|
||||
.8byte tx_data, 0x000000CE, write32_test # place data into tx_data
|
||||
.8byte cs_id, 0x00000001, write32_test #change selected cs pin. should deassert cs[0] in hold mode
|
||||
.8byte cs_def, 0x00001101, write32_test # change selected cs pins def value. should deassert cs[1]
|
||||
.8byte cs_def, 0x00001111, write32_test # reset cs_def
|
||||
.8byte cs_mode, 0x00000000, write32_test # change cs_mode to auto, should deassert cs[1], have now gone through all deassertion conditions
|
||||
.8byte rx_data, 0x000000CE, read32_test # clear rx_fifo
|
||||
|
||||
# Test transmit and receive fifo full edge cases
|
||||
|
||||
|
||||
# =========== Test frame format (fmt) register ===========
|
||||
|
||||
# Test frame length of 4
|
||||
|
||||
.8byte delay1, 0x00000001, write32_test # reset delay1 register
|
||||
.8byte delay0, 0x00010001, write32_test # reset delay0 register
|
||||
|
||||
.8byte sck_mode, 0x00000000, write32_test #reset sckmode register
|
||||
.8byte cs_mode, 0x00000000, write32_test # set cs_mode to AUTO
|
||||
.8byte fmt, 0x00040000, write32_test # set frame length to 4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user