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correct exclusion tags and reset testbench

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naichewa 2023-11-01 10:34:39 -07:00
parent 8027a71e86
commit b59abc2dcc
3 changed files with 12 additions and 12 deletions
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8
src/mmu/pmachecker.sv
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@ -62,13 +62,13 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
// Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
// I/O is nonidempotent. PBMT can override PMA; NC is idempotent and IO is non-idempotent
assign IdempotentRegion = SelRegions[11] | SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7];
assign Idempotent = (PBMemoryType == 2'b00) ? IdempotentRegion : (PBMemoryType == 2'b01); // exclusion-tag: unused-idempotent
assign IdempotentRegion = SelRegions[11] | SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7]; // exclusion-tag: unused-idempotent
assign Idempotent = (PBMemoryType == 2'b00) ? IdempotentRegion : (PBMemoryType == 2'b01);
// Atomic operations are only allowed on RAM
assign AtomicAllowed = SelRegions[11] | SelRegions[9] | SelRegions[7];
assign AtomicAllowed = SelRegions[11] | SelRegions[9] | SelRegions[7]; // exclusion-tag: unused-idempotent
// Check if tightly integrated memories are selected
assign SelTIM = SelRegions[11] | SelRegions[10];
assign SelTIM = SelRegions[11] | SelRegions[10]; // exclusion-tag: unused-idempotent
// Detect access faults
assign PMAAccessFault = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed;

4
testbench/testbench.sv
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@ -159,7 +159,7 @@ module testbench;
end
if (tests.size() == 0) begin
$display("TEST %s not supported in this configuration", TEST);
//$stop;
$stop;
end
end // initial begin
@ -511,7 +511,7 @@ module testbench;
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
//$stop; //***debug
$stop; //***debug
end
i = i + 1;
end

12
testbench/tests.vh
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@ -2004,12 +2004,12 @@ string arch64zbs[] = '{
string wally64periph[] = '{
`WALLYTEST,
//"rv64i_m/privilege/src/WALLY-periph-01.S",
//"rv64i_m/privilege/src/WALLY-clint-01.S",
//"rv64i_m/privilege/src/WALLY-gpio-01.S",
//"rv64i_m/privilege/src/WALLY-plic-01.S",
//"rv64i_m/privilege/src/WALLY-plic-s-01.S",
//"rv64i_m/privilege/src/WALLY-uart-01.S",
"rv64i_m/privilege/src/WALLY-periph-01.S",
"rv64i_m/privilege/src/WALLY-clint-01.S",
"rv64i_m/privilege/src/WALLY-gpio-01.S",
"rv64i_m/privilege/src/WALLY-plic-01.S",
"rv64i_m/privilege/src/WALLY-plic-s-01.S",
"rv64i_m/privilege/src/WALLY-uart-01.S",
"rv64i_m/privilege/src/WALLY-spi-01.S"
};