430 Commits

Author	SHA1	Message	Date
David Harris	4cde207958	Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression.	2023-03-18 10:10:58 -07:00
David Harris	f53b2f6e1f	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-18 09:24:37 -07:00
David Harris	6922298f21	Replaced FenceM with InvalidateICacheM for event counting of fence.i	2023-03-18 09:24:31 -07:00
Ross Thompson	3d37d2769a	Book updates.	2023-03-14 13:09:50 -05:00
Ross Thompson	3cae6ca90f	Updated NextAdr to NextSet.	2023-03-13 14:54:13 -05:00
Ross Thompson	c190444fa2	Updated CAdr to CacheSet.	2023-03-13 14:53:00 -05:00
Ross Thompson	ada099c58b	Changes BTA to BPBTA.	2023-03-12 14:36:46 -05:00
Ross Thompson	a5523400ae	Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.	2023-03-12 13:21:22 -05:00
Kevin Kim	0d0d3b981e	more checks in bitmanip decode	2023-03-10 17:17:24 -08:00
Kevin Kim	9b4f3219db	formatting	2023-03-10 14:32:01 -08:00
Kevin Kim	c380b0816d	removed redundant convinvb signal	2023-03-10 14:18:24 -08:00
Kevin Kim	dcaf9de228	removed redundant condinvb mux	2023-03-10 14:17:38 -08:00
David Harris	f411803bc4	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-10 12:47:30 -08:00
David Harris	33fa7e4706	Simplified SLT and SLTU code in ALU	2023-03-09 15:14:52 -08:00
Kevin Kim	f29e8932a2	more comprehensive illegal b instr. check	2023-03-09 12:44:51 -08:00
Kevin Kim	f335d08bbf	fixed bmu bug ... - accidentally deleted count instruction decode	2023-03-09 12:35:42 -08:00
Ross Thompson	68b437ce92	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-09 13:29:38 -06:00
Kevin Kim	260dcc8b96	Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip	2023-03-08 16:22:47 -08:00
Kevin Kim	7002221dec	cleaner bmu decode logic	2023-03-08 16:22:43 -08:00
Ross Thompson	4db17cde2f	Updated testbench to record coremark performance counters. ... Added comment about mtval probably not being correct for compressed instructions.	2023-03-08 17:11:27 -06:00
kipmacsaigoren	2337e2ae16	Merge branch 'openhwgroup:main' into bit-manip	2023-03-07 21:29:03 -08:00
David Harris	88c3a61cd7	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-07 14:49:23 -08:00
Kevin Kim	0ca530fffd	Merge branch 'bit-manip' into illegal_specific	2023-03-07 14:07:59 -08:00
Kevin Kim	f29bbe5f69	Merge branch 'openhwgroup:main' into illegal_specific	2023-03-07 14:06:22 -08:00
Kevin Kim	4bb43892f9	alu formatting	2023-03-07 14:01:47 -08:00
Kevin Kim	26cb1857f3	specifc instruction handling for B's ... - Added BALUSrcBD, BaseALUSrcB for distinguishing between base instruction I/IW and Bitmanip instruction I/IW	2023-03-07 13:58:08 -08:00
kipmacsaigoren	24f0f34aff	Merge branch 'openhwgroup:main' into priv-tests	2023-03-07 13:46:55 -08:00
Kip Macsai-Goren	f28a284e5e	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-03-07 13:45:04 -08:00
Kip Macsai-Goren	2ec3c741ef	Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip	2023-03-07 13:44:51 -08:00
Kip Macsai-Goren	f178c90c02	Merge branch 'main' of github.com:kipmacsaigoren/cvw into bit-manip	2023-03-07 13:44:19 -08:00
Kevin Kim	bd9b9970f5	Merge remote-tracking branch 'origin' into illegal_specific	2023-03-07 11:30:36 -08:00
Kevin Kim	6d146a7e20	formatting	2023-03-07 10:57:52 -08:00
Kevin Kim	833e7bd2af	shifter sign generation logic optimize	2023-03-07 10:57:06 -08:00
David Harris	77ba71be71	editorconfig to specify tabs/spaces. Fixed some tabs. Turn off coverage to speed up simulation	2023-03-07 06:31:40 -08:00
Kevin Kim	81198ce6f6	reverted backing to working version	2023-03-07 00:29:58 -08:00
Kevin Kim	5637897dce	reverted to working version	2023-03-07 00:28:07 -08:00
Ross Thompson	6d4e28fdf2	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-06 22:29:27 -06:00
Ross Thompson	e448cd54ef	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-03-06 18:39:15 -06:00
Ross Thompson	a6b851a672	Renamed signals to be consistent with textbook.	2023-03-06 18:29:31 -06:00
Ross Thompson	31fcc0daf7	Renamed PCFSpill to PCSpillF.	2023-03-06 17:50:57 -06:00
Ross Thompson	473ed2b475	Renamed InstrFirstHalf to InstrFirstHalfF.	2023-03-06 17:48:57 -06:00
Ross Thompson	fdfb80a818	Renamed ebuarbfsm to ebufsmarb to match figures.	2023-03-06 17:47:55 -06:00
David Harris	7ecf4cdea8	Fixed bug about rv64 shifts only using 6 bits of funct7	2023-03-06 13:10:51 -08:00
David Harris	7e0c96cdcc	Simplified decoder default to illegal instruction	2023-03-06 11:21:11 -08:00
David Harris	c2efdbdbbb	More detailed decoding of load/store/branch/jump	2023-03-06 11:15:48 -08:00
David Harris	a56557d847	Improved decoding illegal instructions in controller	2023-03-06 11:02:42 -08:00
Kevin Kim	c7d1e35d4a	structural changes in cnt.sv	2023-03-06 06:44:15 -08:00
Kevin Kim	e67b02136c	formatting	2023-03-06 06:20:25 -08:00
Kevin Kim	ee66b5fb4a	formatting ... - reverted back to ALUResult signal in alu.sv	2023-03-06 06:19:01 -08:00
Kevin Kim	8f3acedec8	formatted files	2023-03-06 05:52:08 -08:00
Kevin Kim	fb529e1640	updated license header	2023-03-06 05:41:53 -08:00
Kevin Kim	e80c1248a2	bug fix	2023-03-05 15:20:48 -08:00
Kevin Kim	3dbdf3d579	extend unit structural mux	2023-03-05 15:09:02 -08:00
Kevin Kim	696cfb6949	zbb result select mux structural	2023-03-05 14:57:30 -08:00
Kevin Kim	2ae32f75b5	zbc input mux structural	2023-03-05 14:26:31 -08:00
Kevin Kim	77d8f10574	revA signals to cnt, zbb	2023-03-05 14:26:24 -08:00
Kevin Kim	7836bc1e37	ALU changes ... - added PreShiftAmt signal for shadd - condinvB now muxes from B instead of mask	2023-03-05 14:06:24 -08:00
Kevin Kim	0f2360f0d7	bug in bctrl ... - deleted the min/minu decoding for some reason.	2023-03-04 23:56:33 -08:00
Kevin Kim	6b25c64a1f	BSelect from OH encoding to Binary	2023-03-04 23:19:31 -08:00
Kevin Kim	a293c350ba	alu pre-shift ... -changed ALU pre shift logic to use a 2 bit shifter instead of mux	2023-03-04 23:07:06 -08:00
Kevin Kim	7512e55699	added python script ... -I've been using this python script to make quick changes to the bitmanip controller	2023-03-04 22:54:32 -08:00
Kevin Kim	294e024c9b	Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip	2023-03-04 22:44:09 -08:00
Kevin Kim	9494cf9340	removed rotate signal in datapath and instead packed into the new BALUControl Signal ... - BALUControl contains Rotate, Mask, PreShift signals to select from the respective generation muxes in the ALU	2023-03-04 22:44:03 -08:00
Kip Macsai-Goren	a38f7cc8a1	added reset values to stime and stimecmp registers	2023-03-04 15:06:15 -08:00
Kip Macsai-Goren	4cede344a1	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-03-04 14:43:12 -08:00
Kevin Kim	f5dca0bf4f	zbc result mux is now structural	2023-03-04 09:22:21 -08:00
Kevin Kim	72de867e65	Rotate signal now gets generated in bmu ctrl	2023-03-03 22:57:49 -08:00
Kevin Kim	b315066b03	license comments	2023-03-03 21:52:34 -08:00
Kevin Kim	0403cfd41a	removed redundant signals in controller	2023-03-03 21:52:25 -08:00
Kevin Kim	8dd39fbcfb	b controller generates comparison signed flag and controller branch signed logic updated accordingly	2023-03-03 17:12:29 -08:00
Ross Thompson	da74ed0369	Merge pull request #126 from davidharrishmc/dev ... ImperasDV setup	2023-03-03 18:01:32 -06:00
David Harris	876c33da5f	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-03 15:54:42 -08:00
Kevin Kim	5e01f86bc5	sltD signal debug. Passes regression	2023-03-03 12:44:33 -08:00
Kevin Kim	c836eea17c	sltD logic optimize	2023-03-03 12:35:40 -08:00
Kevin Kim	d6f8c1dd29	Merge branch 'bctrlmigrate' of https://github.com/kipmacsaigoren/cvw into bctrlmigrate	2023-03-03 09:54:08 -08:00
Kevin Kim	1c55d4a8d5	Merge branch 'openhwgroup:main' into bctrlmigrate	2023-03-03 09:53:59 -08:00
Kevin Kim	422b428cba	removed outdated b-signals in controller	2023-03-03 08:45:42 -08:00
Kevin Kim	9cad890c1a	comments to bctrl	2023-03-03 08:41:47 -08:00
Kevin Kim	19410b4196	migrated B-subarith logic into b controller	2023-03-03 08:40:29 -08:00
Kevin Kim	2c3271dd62	began subarith configurability optimization in controller	2023-03-03 08:27:11 -08:00
Ross Thompson	0cb5369351	Renamed BTB misprediction to BTA.	2023-03-03 00:18:34 -06:00
Ross Thompson	5b5677ccb8	Added divide cycle counter.	2023-03-02 23:59:52 -06:00
Ross Thompson	aabb454d1c	Added the i and d cache cycle counters.	2023-03-02 23:54:56 -06:00
Ross Thompson	cfca77172e	Added fence counter.	2023-03-02 23:29:20 -06:00
Ross Thompson	f32f8c109a	Added csr write counter, sfence vma counter, interrupt counter, and exception counter.	2023-03-02 23:21:29 -06:00
Ross Thompson	a313b10912	Added store stall to performance counters.	2023-03-02 23:10:54 -06:00
Ross Thompson	2dd693a3b3	Reordered performance counters and added space for new ones.	2023-03-02 23:04:31 -06:00
David Harris	316b8b2250	Refactored Floating point division special case detection to avoid spurious trigger on Y for sqrt)	2023-03-02 20:00:47 -08:00
Kevin Kim	b21ca2fba0	bug fix, more elegant logic changes in controller	2023-03-02 16:00:56 -08:00
Kevin Kim	c9bd37c92b	formatting	2023-03-02 15:28:43 -08:00
Kevin Kim	910eeea3ff	removed main instruction decoder dependence on bmu controller	2023-03-02 15:28:33 -08:00
Kevin Kim	05b329dd6a	added bitmanip illegal instruction signal	2023-03-02 15:09:55 -08:00
Kevin Kim	3e8e633a56	zbc comments	2023-03-02 13:52:00 -08:00
Kevin Kim	b0307f5082	formatted bmu decoder	2023-03-02 13:45:15 -08:00
Kevin Kim	24b0b83d52	moved ALUControlD into configurable block	2023-03-02 12:17:03 -08:00
Kevin Kim	0f60505179	moved SubArith and RegWriteE into configurable block	2023-03-02 12:15:57 -08:00
Kevin Kim	b81a5e4452	added BRegWriteE signal	2023-03-02 12:15:22 -08:00
Kevin Kim	5e10720bed	rename shifternew to shifter	2023-03-02 11:45:32 -08:00
Kevin Kim	cf324510f3	zbc input select mux optimize	2023-03-02 11:43:05 -08:00
Kevin Kim	657719220a	zbc select mux optimization	2023-03-02 11:40:29 -08:00
Kevin Kim	e62a752522	fixed controller lint, changed byte unit mux select name and input width	2023-03-02 11:36:12 -08:00
Kevin Kim	a5e2e24320	removed redundant zbs	2023-03-02 11:22:09 -08:00
Ross Thompson	b98e007a53	Cleaned up branch predictor performance counters.	2023-03-01 17:05:42 -06:00
David Harris	5c8c50adba	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-03-01 11:18:05 -08:00
David Harris	23775c6d67	Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA	2023-03-01 11:18:00 -08:00
Ross Thompson	90b2f0a652	Set bp to use instruction class prediction by default.	2023-03-01 11:52:42 -06:00
Ross Thompson	dea6b643a6	Branch predictor cleanup. ... I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.	2023-03-01 11:24:24 -06:00
Ross Thompson	03a6679ba0	More btb cleanup.	2023-03-01 10:47:00 -06:00
Ross Thompson	554e7d0973	Minor fix to btb.	2023-03-01 10:45:40 -06:00
Ross Thompson	a6917d07f3	Name cleanup.	2023-02-28 17:48:58 -06:00
Kip Macsai-Goren	58ab6ec805	Merge remote-tracking branch 'upstream/main' into bit-manip	2023-02-28 14:41:51 -08:00
Kip Macsai-Goren	f63748f097	Merge remote-tracking branch 'origin' into bit-manip	2023-02-28 14:39:57 -08:00
Ross Thompson	4c0e7f297a	Found the performance bug with the branch predictor btb power saving update.	2023-02-28 15:57:34 -06:00
Ross Thompson	2ebe600f54	Name changes to reflect diagrams.	2023-02-28 15:37:25 -06:00
Ross Thompson	be4823f7dd	Undid the btb update as it reduces performance.	2023-02-28 15:21:56 -06:00
Kevin Kim	df0d75034b	bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG]	2023-02-28 12:09:35 -08:00
Kevin Kim	b61d881c1b	added BRegWrite, BW64, BALUOp signals to bctrl and controller ... -TODO: Main decode in bmuctrl must assert these 3 signals	2023-02-28 11:54:10 -08:00
Kevin Kim	692e406976	changed shifter source select signal name	2023-02-28 11:41:40 -08:00
Kevin Kim	1506d50c63	rename result back to ALUResult in ALU	2023-02-28 07:27:34 -08:00
Ross Thompson	9dd3379744	This icpred and btb changes are causing a performance issue.	2023-02-27 20:00:50 -06:00
Ross Thompson	544abe2819	Modified the BTB to save power by not updating when the prediction is unchanged.	2023-02-27 17:37:29 -06:00
Ross Thompson	bc5aecf948	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-27 09:48:03 -06:00
David Harris	cf8b5f0783	Added support for ZMMUL	2023-02-27 07:29:53 -08:00
Ross Thompson	318189e5e6	Signal name changes.	2023-02-27 00:39:19 -06:00
David Harris	f40352e82b	hptw typo fix	2023-02-26 19:38:34 -08:00
Ross Thompson	c89812b2d4	Branch predictor cleanup.	2023-02-26 21:28:36 -06:00
David Harris	e9ad6ae057	Simplified Access fault logic in HPTW	2023-02-26 18:50:37 -08:00
David Harris	2d7145901b	StoreAmo faults are generated instead of load faults on AMO operations	2023-02-26 18:35:10 -08:00
Ross Thompson	e8c5e5b5ff	Create module for instruction class prediction and decoding.	2023-02-26 20:20:30 -06:00
Ross Thompson	3964ce3309	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2023-02-26 19:58:24 -06:00
David Harris	21b28fd1bb	Renamed DAPageFault to UpdateDA	2023-02-26 17:51:45 -08:00
David Harris	4274071333	renamed UpperBitsUnequalPageFault to UpperBitsUnequal	2023-02-26 17:32:34 -08:00
David Harris	06bd4783af	moved tlb to subdirectory	2023-02-26 17:31:03 -08:00
David Harris	c774b44116	Moved TLB into subdirectory of MMU	2023-02-26 17:28:05 -08:00
Ross Thompson	72be4318b8	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2023-02-26 12:06:06 -06:00
David Harris	dc447ed5ed	Removed unneeded TLBFlush from TLBMiss	2023-02-26 10:04:16 -08:00
David Harris	54b8e7c629	Access faults are geted by ~TLBMiss rather than ~(Translate & ~TLBHit)	2023-02-26 09:58:34 -08:00
David Harris	35653a18b7	Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED	2023-02-26 09:38:32 -08:00
David Harris	f31764c3e1	Renamed DAPageFault to HPTWDAPageFault in hptw to avoid name conflict with DAPageFault from tlbcontrol	2023-02-26 07:12:43 -08:00
David Harris	fe161f6bde	Fixed missing assign when SSTC is not supported	2023-02-26 07:12:13 -08:00
David Harris	8895114152	Fixed SSTC being unusable in M-MODE without Status.TM. Disable STIMECMP registers when SSTC_SUPPORTED = 0	2023-02-26 06:30:43 -08:00
Ross Thompson	7f8034013d	PHT was enabled using the wrong ~flush and ~stall.	2023-02-24 22:57:32 -06:00
Ross Thompson	eb9dc7e67d	gshare cleanup.	2023-02-24 22:55:51 -06:00
Ross Thompson	9df05f0b3d	More signal renames.	2023-02-24 19:56:55 -06:00
Ross Thompson	8bd4a4c35b	Renamed signals to match new figures.	2023-02-24 19:51:47 -06:00
Kevin Kim	f5d3e0e8a0	removed old shifter	2023-02-24 17:33:47 -08:00
Ross Thompson	f95f326b3d	Renamed signals to match figure 10.18.	2023-02-24 19:22:14 -06:00
Kevin Kim	601c6fcdc4	removed now-redundant zero-extend mux in alu	2023-02-24 17:14:12 -08:00
Kevin Kim	1d4200e3a3	took sign extension out of shifter	2023-02-24 17:09:56 -08:00
Ross Thompson	40a164a8da	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-24 18:50:35 -06:00