Noah Boorstin
932bc0ef85
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
0596d61a2a
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
kaveh pezeshki
e8b306bcba
merged with main to integrate with AHB
2021-02-26 05:37:10 -08:00
Noah Boorstin
4c7b185d90
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
kaveh Pezeshki
2782ca2480
fixed sensitivity list on error checking always block, removed useless once and for all
2021-02-26 13:41:16 -05:00
kaveh pezeshki
adadc21fc6
restored
2021-02-26 02:22:08 -08:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
kaveh pezeshki
251aa982eb
condensed always blocks to avoid race conditions
2021-02-24 11:35:28 -08:00
Noah Boorstin
ddaf67c043
busybear: preload bootram
...
thanks to Prof Stine for the .do file commands
@kaveh can you check line 201? it does nothing, but things break when
I remove that line
2021-02-24 18:46:09 +00:00
David Harris
38b8cc652c
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
kaveh pezeshki
06f73fe5fe
added comments for RAM and bootram, removed trailing whitepace
2021-02-23 21:28:33 -08:00
Noah Boorstin
b7f4e72eec
busybear: add bootram section in the same manner as ram
2021-02-24 02:02:28 +00:00
Noah Boorstin
914a36e3e8
busybear: add support for subwords in ram
...
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
2021-02-24 01:51:18 +00:00
Noah Boorstin
7b7e87bd0b
busybear: start adding ram
2021-02-23 22:01:23 +00:00
Noah Boorstin
5394d38e4a
busybear: remove unused signals
2021-02-23 19:38:19 +00:00
Noah Boorstin
c42c485377
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
David Harris
7737b0f709
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8
Debugging Bus interface
2021-02-22 13:48:30 -05:00
kaveh pezeshki
e146946e58
Merge remote-tracking branch 'origin/tlb_toy' into busybear
2021-02-22 02:23:01 -08:00
David Harris
a7dd20b388
Multiply instructions working
2021-02-17 15:29:20 -05:00
Noah Boorstin
43f9abdbed
busybear testbench: check (almost) all the CSRs
2021-02-16 20:03:24 -05:00
David Harris
adc5d5bc1a
Added MUL
2021-02-15 22:27:35 -05:00
Domenico Ottolia
3ee975dd5a
Add privileged test cases
2021-02-14 17:01:46 -05:00
Shreya Sanghai
4e887f83a3
added branch tests
2021-02-12 22:40:08 -05:00
Noah Boorstin
84d856d1e5
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
Noah Boorstin
dd3a5b74a1
busybear: slightly neater error handling
2021-02-12 17:21:56 +00:00
bbracker
deb7780897
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Noah Boorstin
79fb83409f
bump into virtual/physcial memory?
2021-02-11 23:06:12 -05:00
Noah Boorstin
e89af96bc0
busybear: more updates
...
now gets to instruction 839037 before failing
also updates to match new gdb output format
umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
2021-02-11 22:42:58 -05:00
Tejus Rao
fb6a4bbbf0
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
5f84ed407c
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
ethan-falicov
7925fe3131
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
06517631cc
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
863796b3c1
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
67662b888e
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
David Harris
b121b90b28
Debugging bus interface.
2021-02-10 01:43:54 -05:00
David Harris
842c374de9
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
Jarred Allen
e334475ab5
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
805817cda4
merge conflict?
2021-02-07 02:34:49 -05:00
Noah Boorstin
01b1b1705d
Busybear: next week of updates
...
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
- parsed first 1M instructions, and now parse from split GDB runs
- now at about 230k instructions, can't progress further for now since atomic instructions
aren't implemented yet
2021-02-07 03:14:48 +00:00
Jarred Allen
29b7a0cd25
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
bbracker
15c0b4af22
JAL testing
2021-02-05 08:08:42 -05:00
Thomas Fleming
8d7a515ae7
Complete STORE tests
2021-02-04 15:38:22 -05:00
Noah Boorstin
fc734eb14e
busybear: add more CSRs
2021-02-04 20:13:36 +00:00
Noah Boorstin
77a88d8019
busybear: check initial values also
2021-02-04 19:22:09 +00:00
Noah Boorstin
f1768ee50b
Busybear: start checking CSRs
...
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)
and 3 of the CSRs referenced are skipped because of weird locations for them
oh and this doesn't check their initial state, just their changing. This could be a problem
2021-02-02 06:06:03 +00:00
Noah Boorstin
38265c03b7
busybear: start adding CSR checking
...
@kaveh is there a less verbose way to do this?
2021-02-01 22:08:51 -05:00
Noah Boorstin
d592db79c9
busybear: change register file checking to only store register changed
...
this should make parsedRegs.txt much smaller
2021-02-02 01:27:43 +00:00
