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1852 Commits

Author SHA1 Message Date
Cedar Turek
21b2ea9666 fpu passing idiv tests on rv32gc 1 copy of radix 2! 2022-12-26 21:47:56 -08:00
Cedar Turek
6977b7ceac took out otfc swap. updated postprocessing quotient/remainder logic for int div. 2022-12-26 21:03:56 -08:00
David Harris
add381a09e Fixed early termination for square root 2022-12-26 08:54:57 -08:00
David Harris
71f214df20 Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
David Harris
3eafd2cca1 Removed unused DivSE from FPU 2022-12-26 07:29:19 -08:00
David Harris
214ef40b1c Moved floating-point tests earlier in Wally config 2022-12-25 22:31:20 -08:00
David Harris
0a067d342f Restored missing floating point load/store tests 2022-12-25 22:28:14 -08:00
David Harris
1a7c7a36d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-25 20:12:55 -08:00
Ross Thompson
1d11ff6153 Added missing assignment for no branch predictor mode. 2022-12-24 17:08:29 -06:00
David Harris
ac4797aac4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-24 12:24:38 -08:00
Ross Thompson
b14b71c7a9 Fixed bug with the performance counters not updating. 2022-12-24 14:24:17 -06:00
David Harris
921b5582da ALU cleanup 2022-12-24 07:18:35 -08:00
cturek
ba3aca413c Added A Sign register. Fixed postprocessing logic for postinc and rem calculation. 2022-12-24 06:46:52 +00:00
Ross Thompson
693f32973f Minor optimizations. 2022-12-23 20:11:36 -06:00
Ross Thompson
424012ce97 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-23 19:51:23 -06:00
Katherine Parry
66510f38af reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
f4f68cdd19 Improved comment. 2022-12-23 15:13:15 -06:00
Ross Thompson
b5a85b55f1 Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
c9c83ca5ae Removed XEnE, YEnE, and ZEnE from forward logic. 
Cleanup comments.
 2022-12-23 14:27:03 -06:00
Ross Thompson
deee433d07 Cleanup floating point hazard logic. 2022-12-23 14:21:47 -06:00
Ross Thompson
c8a0e7685a DON'T USE. First commit in attempt to move fpustall detection into the decode stage. 2022-12-23 12:47:18 -06:00
Ross Thompson
b1aa370ff1 Removed ZForwardEnE and replaced with ZEnE. 
Similar for YForwardEnE.
 2022-12-23 12:27:51 -06:00
Ross Thompson
30dd86d146 Removed unnecessary stall when MatchDE was driven 1 by RdE == 0. 2022-12-23 11:45:42 -06:00
David Harris
98ecd9c77d Commented out fdiv early termination - broke fsqrt test 2022-12-23 00:58:55 -08:00
David Harris
04dd3e5144 Fixed early termination on fdivsqrt 2022-12-23 00:53:55 -08:00
David Harris
1f6dc62bb3 Moved InstrValidNotFLushed to csr including InstrValidM 2022-12-23 00:27:44 -08:00
David Harris
85d0b697bf Removed unused StallW from CSRs 2022-12-23 00:21:36 -08:00
David Harris
fe5b9081d9 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
93bb8036be Revert to 98b824 2022-12-22 23:58:14 -08:00
David Harris
a185f563f2 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
David Harris
74979cdc82 FDIV merge 2022-12-22 23:03:03 -08:00
David Harris
51b92285d3 Removed unused signals in FPU and CSR 2022-12-22 22:59:05 -08:00
Ross Thompson
b6b30533e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-22 22:51:33 -06:00
Ross Thompson
6b105bd217 Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
5a9e94048a The LSU is properly using FlushW rather than TrapM. 2022-12-22 21:47:34 -06:00
Ross Thompson
ce7e1073fa Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
Ross Thompson
677f6f8737 Partial cleanup for BP. 2022-12-22 20:33:38 -06:00
Ross Thompson
942acb354e Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Ross Thompson
7a0b3d4fc6 Wavefile updates. 2022-12-22 19:45:02 -06:00
Kip Macsai-Goren
d25d699800 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Ross Thompson
47d61984ad First pass at resolving ifu flush on trap rather than FlushD. 2022-12-22 15:53:06 -06:00
David Harris
567f76c2a5 Code cleanup 2022-12-22 10:04:50 -08:00
cturek
04bc787647 Added negative-result int diviison support in U and UM registers. 13 tests pass! 2022-12-22 16:25:37 +00:00
cturek
1712e69c73 Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
cturek
fa03275cca Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-22 05:45:00 +00:00
cturek
c7d0c8823f Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc. 2022-12-22 05:44:55 +00:00
David Harris
4f7d9eee95 XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 20:39:38 -08:00
Ross Thompson
b3ff4fe02e CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled. 2022-12-21 22:13:05 -06:00
cturek
c405dcf0cb worked out some bugs with int div cycles 2022-12-22 02:22:01 +00:00
cturek
e441f90b32 Renamed signals to E and M stages, forwarded preprocessed n to fsm 2022-12-22 00:43:27 +00:00
Ross Thompson
d1aa5ba890 Updated cache fsm names to match book. 2022-12-21 16:49:53 -06:00
Ross Thompson
de161c675c Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-21 16:13:09 -06:00
Ross Thompson
0cb2cf9a5b Changed GatedStallF to GatedStallD. 2022-12-21 16:12:55 -06:00
David Harris
16c8655161 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 14:12:25 -08:00
David Harris
a5dc09c97f Added assertion about atomics needing caches 2022-12-21 13:57:28 -08:00
cturek
2c58fd42db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 20:41:38 +00:00
David Harris
3562542728 comment cleanup 2022-12-21 12:39:09 -08:00
David Harris
ca949f2110 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
cturek
14d9118802 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 19:35:57 +00:00
cturek
6761101645 fixed normshift calculations 2022-12-21 19:35:47 +00:00
David Harris
998f446e3c git push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-12-21 11:31:27 -08:00
David Harris
820e1ab510 Removed unused FPU signals 2022-12-21 11:31:22 -08:00
Ross Thompson
f6393d1288 Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
Ross Thompson
2b1e9f8bed The optimzied PC+2/4 logic still hanges on wally32priv. 2022-12-21 09:19:34 -06:00
Ross Thompson
a2329c8e9d Renamed PCPlusUpperF to PCPlus4F. 2022-12-21 09:18:30 -06:00
Ross Thompson
a6ffb4cef3 Added timeout check to testbench. 
A watchdog checks the value of PCW.  If it does not change within 1M cycles immediately stop simulation and report an error.
 2022-12-21 09:18:00 -06:00
Ross Thompson
3fc121ef70 Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 
Switched to even simplier PC+2/4 logic.
 2022-12-21 09:00:09 -06:00
Ross Thompson
968e174d68 Changes to wave file. 2022-12-21 08:41:47 -06:00
Ross Thompson
bc5d5e902a Comments about PC+2/4. 2022-12-21 08:35:43 -06:00
David Harris
28085ce8eb Clean up vecgtored interrupts 2022-12-20 16:53:09 -08:00
David Harris
88ee834c97 Converted tvecmux to structural 2022-12-20 16:24:04 -08:00
Ross Thompson
6152c028db Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 18:09:37 -06:00
Ross Thompson
2f0d20b8b0 privileged pc mux cleanup. 2022-12-20 18:05:44 -06:00
Ross Thompson
cba2ed64e5 Moved privileged pc logic into privileged unit. 2022-12-20 17:55:45 -06:00
David Harris
07dc11a508 IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI 2022-12-20 15:38:30 -08:00
Ross Thompson
b4bdf446cc Implement FENCE.I as NOP when ZIFENCEI is not supported. 2022-12-20 17:34:11 -06:00
Ross Thompson
d9a1870a31 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 17:11:35 -06:00
Ross Thompson
ef4ecbe62b Changed long names of vectored pcm signals. 2022-12-20 17:01:20 -06:00
David Harris
f03d4e6b5a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-20 14:43:33 -08:00
David Harris
9133b3a7a4 FPU remove unused signals 2022-12-20 14:43:30 -08:00
Ross Thompson
be1bbf486e Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 16:36:44 -06:00
Ross Thompson
637df763ca Renumbered bits for PCPlusUpper. 2022-12-20 16:33:49 -06:00
David Harris
4c4b8db498 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-20 11:23:53 -08:00
David Harris
8f0ef29349 Memory cleanup 2022-12-20 11:22:26 -08:00
Ross Thompson
ca6076445b Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 12:58:59 -06:00
Ross Thompson
d35fc5e2a6 Reorganized IFU PCNextF logic. 2022-12-20 12:58:54 -06:00
David Harris
c26c3b76ea Renamed renamed sram to ram 2022-12-20 08:36:45 -08:00
David Harris
1ec62606f9 sram1p1rw cleanup 2022-12-20 02:57:51 -08:00
David Harris
0883736c88 Remoed unused bram modules 2022-12-20 02:40:45 -08:00
David Harris
9ad5552e89 Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:55 -08:00
David Harris
b575f6242e Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:36 -08:00
David Harris
0c10ec942a Replaced || and && with single ops 2022-12-20 01:33:35 -08:00
Ross Thompson
67e0b021ae several options for pcnextf on fence.i 2022-12-19 23:33:12 -06:00
Ross Thompson
d18ef45c18 More bp/ifu pcmux cleanup. 2022-12-19 23:16:58 -06:00
Ross Thompson
761cf54dcc Moved more muxes inside bp. 2022-12-19 22:51:55 -06:00
Ross Thompson
0097c166d6 Begin cleanup of ifu. partial move of pc muxes inside bp. 2022-12-19 22:46:11 -06:00
David Harris
954051da13 Removed CSR support from rv32i 2022-12-19 16:15:12 -08:00
David Harris
2393915bf2 Simplified InstrRawD register 2022-12-19 15:18:42 -08:00
David Harris
aac4b55b59 Explained hazard causes 2022-12-19 09:41:41 -08:00
David Harris
16b8fbbd2d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-19 09:09:57 -08:00
David Harris
b5958b1e11 Properly decode fcvtint to prevent unnecessary stalls 2022-12-19 09:09:48 -08:00
Ross Thompson
ddde82f928 Renamed FStallD to FPUStallD. 2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
13c9f2e4a5 Added NumZeroE, AZeroM, and BZeroM 2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
3bcb42adb6 fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8) 2022-12-18 19:04:36 -08:00
Ross Thompson
c3b77926d5 I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
7a352edf13 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
9d1cb9337e Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
Ross Thompson
5acdf541b9 Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back. 2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348 At long last found the subtle bug in the LRU. 
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
 2022-12-17 10:03:08 -06:00
Ross Thompson
c985988867 Fixed a bug with the new cache flush changes. 2022-12-16 19:28:32 -06:00
Ross Thompson
9b9e954cc5 Cleanup comments. 2022-12-16 17:08:35 -06:00
Ross Thompson
5f556817c7 Further cleanfsm cleanup. 2022-12-16 16:37:45 -06:00
Ross Thompson
493b1a4280 More cachefsm cache flush cleanup. 2022-12-16 16:32:21 -06:00
Ross Thompson
3132246a46 Oups found a bug with the new flush cache states. 2022-12-16 16:22:40 -06:00
Ross Thompson
698ca7d482 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-16 15:37:03 -06:00
Ross Thompson
91e64a0d67 Cleanup of cache flush fsm enhancement. 2022-12-16 15:36:53 -06:00
Ross Thompson
ab3c5a0ca7 Rough draft of cache flush fsm enhancement. 2022-12-16 15:28:22 -06:00
cturek
0ceecd9961 Added integer support for initC 2022-12-16 19:02:11 +00:00
Ross Thompson
9c67972b21 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-16 12:52:22 -06:00
Ross Thompson
f04ca5cb6a Fixed regression-wally to correct remove and mkdir wkdir. 2022-12-16 12:51:21 -06:00
cturek
9340a5eb49 Added mux for integer special case, renamed signals to match pipelined stage 2022-12-16 18:43:49 +00:00
David Harris
940fd2f924 Clean up interrupt masking by Commit 2022-12-16 08:27:39 -08:00
David Harris
a285f289a6 Disabled starting FPU divider when IDIV_ON_FPU = 0 2022-12-16 06:35:29 -08:00
cturek
9f1aa7ad19 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-16 03:41:39 +00:00
David Harris
da2d68c699 Use FlushE to reset integer divider FSM 2022-12-15 11:00:54 -08:00
David Harris
a8126458f6 Refactored stalls and flushes, including FDIV flush with FlushE 2022-12-15 10:56:18 -08:00
David Harris
97a432570a Regression delete wkdir files to prevent spurious failures 2022-12-15 10:24:58 -08:00
David Harris
3bef12b108 Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE 2022-12-15 08:23:34 -08:00
Ross Thompson
8cd6a74c8f Hazard cleanup. 2022-12-15 10:05:17 -06:00
Ross Thompson
c253b882be Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
Ross Thompson
0358a8d255 Merge branch 'main' into hazards 2022-12-15 08:44:59 -06:00
David Harris
e80e84aace Added IDIV_ON_FPU flag to control whether integer division uses FPU 2022-12-15 06:37:55 -08:00
David Harris
643a2e7cf9 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
cturek
482caec42d Fixed BZero and initU/initUM muxes 2022-12-14 16:44:46 +00:00
Ross Thompson
4a0e4aed99 Signal renames to reflect figures. 2022-12-14 09:49:15 -06:00
Ross Thompson
8f04f2d9e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-14 09:34:34 -06:00
Ross Thompson
b69aa39f30 Reduced complexity of linebytemask. 2022-12-14 09:34:29 -06:00
cturek
e4c1bb2bff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-14 15:13:44 +00:00
Ross Thompson
0f0fed2496 Broken dont' use. 2022-12-11 23:24:01 -06:00
Ross Thompson
dbc3dac03d Removed unused flushf. 2022-12-11 16:28:11 -06:00
Ross Thompson
ad7dd56180 Renamed CPUBusy to GatedStallF in IFU. 2022-12-11 15:54:19 -06:00
Ross Thompson
5b38b4e639 Renamed CPUBusy in LSU. 2022-12-11 15:52:51 -06:00
Ross Thompson
6d573b32d2 Changed CPUBusy to Stall in ebu modules. 2022-12-11 15:51:35 -06:00
Ross Thompson
232f866ad1 Renamed CPUBusy to Stall in cache. 2022-12-11 15:49:34 -06:00
Ross Thompson
a58fbd618e Moved CPUBusy out of HPTW. 2022-12-11 15:48:00 -06:00
cturek
930fcbe956 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Ross Thompson
d3b2e331c2 Added comments about why it is not possible to use FlushWay and VictimWay directly. 2022-12-09 17:07:35 -06:00
Ross Thompson
f09b9e1572 Finished merge of kip and ross's ifu fix. 2022-12-09 16:52:22 -06:00
Ross Thompson
981ac3963a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-09 16:42:16 -06:00