cturek
54f09f3616
Added conditional OTFC swap for simplified int postprocessing
2022-11-06 23:09:09 +00:00
cturek
83051a5351
Changed lzc names, started int/fp size merge in preproc
2022-11-06 22:21:35 +00:00
cturek
6bc4c1318e
Added new macros for int div preprocessing, added p, n, and rightshiftx logic
2022-11-06 21:53:48 +00:00
cturek
9f41e57f03
Config Cleanup
2022-10-27 22:38:56 +00:00
cturek
71d16eacef
unbroke DIVb
2022-10-26 16:11:51 +00:00
cturek
1febdb75b7
Config cleanup
2022-10-25 21:04:09 +00:00
Ross Thompson
dfd07a57fd
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
31e9af0eb2
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
9d23b0e6d6
Reorganized the configs.
2022-10-09 16:46:48 -05:00
David Harris
29033dc334
Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.
2022-10-05 11:46:52 -07:00
David Harris
f7d272c315
Gated sticky bit in fdiv with SpecialCase
2022-09-20 20:05:00 -07:00
David Harris
1cbdd20778
Restored radix 2 to pass regression
2022-09-20 19:30:16 -07:00
cturek
c3c764f0ba
Fixed fgen4
2022-09-20 20:00:01 +00:00
David Harris
11fb39b373
Define LOGNORMSHIFTSZ
2022-09-20 08:31:57 -07:00
David Harris
73ceb4590c
Finished unified divsqrt otfc and fgen name changes
2022-09-19 08:30:59 -07:00
David Harris
f38bb5b32e
Divide testfloat starts with half-precision tests
2022-09-18 06:46:47 -07:00
David Harris
19e449b83d
Fixed regression for divsqrt radix2
2022-09-07 06:12:23 -07:00
David Harris
09456db445
Checking in radix 4 square root with qsel, fgen, softc, but not working
2022-08-31 10:54:50 -07:00
David Harris
e1760dde55
Fixed checking termination in testfloat testbench
2022-08-30 10:55:21 -07:00
David Harris
4aa30c48aa
fixed wally-config
2022-08-26 22:13:10 -07:00
David Harris
37f0b52520
Fixed address decoder hanging buildroot
2022-08-26 22:01:25 -07:00
David Harris
d0dbc74492
Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs
2022-08-26 21:29:26 -07:00
David Harris
2b241f8bbd
Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding
2022-08-26 21:18:18 -07:00
David Harris
03e731b3ff
Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
2022-08-26 21:05:20 -07:00
David Harris
f0b4f69b65
Added IROM and DTIM decoding to adrdecs
2022-08-26 20:45:43 -07:00
David Harris
812158aeee
Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
2022-08-26 20:26:12 -07:00
David Harris
95dd50a567
Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
2022-08-26 20:12:03 -07:00
Ross Thompson
3b612d6201
Possible fixes for earily messup of rv32ic and rv64ic configs.
2022-08-25 14:42:08 -05:00
Ross Thompson
e605ef57dc
BROKEN. Don't use this commit.
...
Issue running cacheless with bus.
2022-08-25 11:02:46 -05:00
Ross Thompson
769af32f2a
Renamed RAM to UNCORE_RAM.
2022-08-24 18:09:07 -05:00
Ross Thompson
51adf6cba9
Modified the lsu/ifu memory configurations.
2022-08-24 12:35:15 -05:00
David Harris
e714b75888
LSU minor edits
2022-08-23 07:35:47 -07:00
Katherine Parry
36be692c0b
sqrt passes - lint warnings remain
2022-08-22 17:16:12 +00:00
Katherine Parry
cb0c1b7488
radix-2 1 copy passes testfloat
2022-08-06 22:54:05 +00:00
Katherine Parry
de6ae471bc
fixed fsw problem and removed 2 bit shift from shift correction
2022-08-03 22:16:51 +00:00
Ross Thompson
69d520a7eb
Removed replay from the config files.
2022-07-24 00:34:11 -05:00
Katherine Parry
b3d932cd61
divider sizes reworked to match book
2022-07-22 22:02:04 +00:00
Katherine Parry
fbe8bb2298
radix-4 division integrated into srt - not tested
2022-07-21 19:38:06 +00:00
Katherine Parry
5cb9c9f319
merged floating-point radix-2 divider with radix-4
2022-07-15 20:16:59 +00:00
cturek
cabd41a5a0
Six tests passing and a bunch of sizizing issues fixed
2022-07-14 19:38:27 +00:00
Katherine Parry
2fe8b6e34c
fixed error in divsqrt
2022-07-14 18:16:00 +00:00
cturek
0b91e7526f
DIVLEN and counter updated for sqrt computation and rounding
2022-07-13 22:42:39 +00:00
cturek
97a1548356
radix 4 files removed from srt and divlen modified for sqrt
2022-07-13 19:46:48 +00:00
Katherine Parry
3c1bea1104
removed warnings and took a mux out of the critical path
2022-07-12 18:32:17 -07:00
Katherine Parry
bea4ec078d
variable interations implemented in radix-4 divider
2022-07-11 18:30:21 -07:00
Katherine Parry
75a8cea4e4
srt divider merged into fpu
2022-07-07 16:01:33 -07:00
Katherine Parry
c581fba4aa
modified wally shared
2022-07-07 21:59:43 +00:00
David Harris
f2915129ab
Preliminary SRAM integration
2022-07-07 19:56:20 +00:00
Katherine Parry
8ac722f693
Renaming signals to match chapter
2022-07-03 12:26:22 -07:00
cturek
7249295f53
Updated radix 2 divider to work with integers and floats in new structure. Integers still might not work.
2022-06-27 23:55:21 +00:00
Katherine Parry
70a1bb8377
fixed commented out error and removed killprod from result selection
2022-06-25 01:42:23 +00:00
slmnemo
528869ef14
Removed references to initialization files
2022-06-23 16:50:27 -07:00
Katherine Parry
de71773d69
added radix-4 0/d handling
2022-06-23 22:36:19 +00:00
Katherine Parry
1612daa294
Testfloat running division - not passing
2022-06-23 00:07:34 +00:00
Katherine Parry
03d823f5d7
added fld in rv32 - needs testing
2022-06-20 22:53:13 +00:00
Katherine Parry
2a8c17170c
hopefully fixed lint error
2022-06-17 00:14:39 +00:00
Katherine Parry
5f7072bd96
postprocessing unit created and passing all tests
2022-06-13 22:47:51 +00:00
DTowersM
4e5d7ec3d6
changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
2022-06-10 00:37:53 +00:00
Katherine Parry
eb93bd46d7
fma synth warnings and errors removed
2022-06-06 16:06:04 +00:00
Katherine Parry
019994c802
removed some debuging code accedentally pushed
2022-06-02 22:45:19 +00:00
Katherine Parry
39101fcbb3
added config rv64fpquad
2022-06-02 22:09:11 +00:00
Katherine Parry
c5bde75e30
added createallvectors
2022-06-02 21:56:05 +00:00
Katherine Parry
ccda4c771e
fpu paramaterized - except fdivsqrt
2022-06-02 19:50:28 +00:00
slmnemo
61f077f62c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-06-02 02:52:03 +00:00
slmnemo
35caa03e46
Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files
2022-06-02 02:51:51 +00:00
Katherine Parry
74b549ddc8
paramerterized some small fma units
2022-06-01 23:34:29 +00:00
Katherine Parry
cc0ab94ebc
Added fp tests - doesnpass yet
2022-05-19 16:32:30 +00:00
slmnemo
ede0a3237d
quit
2022-05-17 01:03:09 +00:00
David Harris
8066ba45e8
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
Kip Macsai-Goren
3d1e1202f3
set WFI timeout to after 16 bits of counting for all configs
2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
da29193f9b
removed atomic, floating point from privileged tests configs
2022-04-25 19:13:15 +00:00
Kip Macsai-Goren
7fe33b2147
Lowered WFI timeout wait time for privileged configs
2022-04-25 17:47:10 +00:00
bbracker
5e76c83309
deprecate unused LINUX_FIX_READ macro
2022-04-21 19:14:47 -07:00
Kip Macsai-Goren
080963c381
fixed rv32ia to support clint and GPIO for priv tests
2022-04-20 17:31:34 +00:00
Shreya Sanghai
c3164f0ce1
added bpred size to wally config
2022-04-18 04:21:03 +00:00
David Harris
2436534687
First implementation of WFI timeout wait
2022-04-17 17:20:35 +00:00
Kip Macsai-Goren
c82667653c
Added missing ZFH macro to new configs
2022-04-06 07:13:51 +00:00
Katherine Parry
20885f4dea
generating all testfloat vectors
2022-04-04 17:17:12 +00:00
Kip Macsai-Goren
cdea062287
added RV64IA config to have a config without compressed instructions
2022-04-02 18:24:08 +00:00
Ross Thompson
57eba4355e
Updated the fpga test bench.
2022-04-01 17:14:47 -05:00
Ross Thompson
6c9750c725
reverted temporary change to configs.
2022-03-22 22:31:34 -05:00
Ross Thompson
600a97982f
Reverted change to configuration which caused issue with lint.
2022-03-22 21:44:08 -05:00
Katherine Parry
2042374102
FMA parameterized and FMA testbench reworked
2022-03-19 19:39:03 +00:00
Ross Thompson
e802deb4d6
Can now support the following memory and bus configurations.
...
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
bbracker
04ace8c154
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
2022-03-01 03:11:43 +00:00
bbracker
6caa97bb26
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
Ross Thompson
6cd9d84e7f
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
13561c67bd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:22:19 -06:00
David Harris
c07584bb70
rv32e config update
2022-02-08 17:59:50 +00:00
Ross Thompson
c2377eaaf4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 11:36:30 -06:00
Ross Thompson
3cd067ac6a
Finished merge.
2022-02-08 11:36:24 -06:00
David Harris
9ad3f26365
Restored E tests to makefrag
2022-02-08 16:41:11 +00:00
David Harris
096242a6d8
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
Ross Thompson
308cc34d6f
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
2022-02-04 23:49:07 -06:00
David Harris
0dd8c719ad
Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
2022-02-05 05:35:51 +00:00
David Harris
23868a33bc
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
David Harris
14c1d86953
rv32e
2022-02-04 01:56:30 +00:00
David Harris
1c049f1f67
renamed configs
2022-02-03 23:36:41 +00:00
David Harris
9e0055cbb9
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
David Harris
bdf1a8ba73
changed DMEM and IMEM configurations to support BUS/TIM/CACHE
2022-02-03 00:41:09 +00:00
