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5,103 Commits 4 Branches 2 Tags 53 MiB
0f13941d3b
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164 Commits

Author SHA1 Message Date
David Harris
0f13941d3b Removed unused BPRED file referenes from fpga config 2023-01-28 20:22:36 -08:00
David Harris
799caef2c9 Renamed BPTYPE to BPRED_TYPE 2023-01-28 20:06:12 -08:00
David Harris
b89fe9989e Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED 2023-01-28 18:52:00 -08:00
David Harris
fa3643a064 Renamed BUS to BUS_SUPPORTED 2023-01-28 18:35:53 -08:00
David Harris
8a96dcf0ae Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED 2023-01-28 18:17:42 -08:00
David Harris
1041775be4 Removed DEISGN_COMPILER configuration paramter 2023-01-28 10:51:39 -08:00
David Harris
5547179a3c Added missing PLIC_GPIO_ID to two config files 2023-01-27 15:23:32 -08:00
David Harris
848ccd8b90 Fixed license header for config files to SolderPad 2023-01-27 15:17:17 -08:00
David Harris
0f68fccf82 Started adding bit manipulation unit 2023-01-20 14:19:07 -08:00
Katherine Parry
4079f76a78 cleaned up all FPU files except for division 2023-01-11 22:02:30 -06:00
David Harris
e6f110b953 Replaced MDUE with IntDivE in FDIVSQRT 2023-01-11 11:06:37 -08:00
David Harris
ddb65ff85f Division constant cleanup 2023-01-10 11:14:59 -08:00
David Harris
080e8884db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-09 13:04:37 -08:00
David Harris
4f4b49886e Changed DIVN from NF+3 to NF+2, cleanup 2023-01-09 13:04:34 -08:00
Ross Thompson
0a77d80224 Added folded gshare predictor with k=16 and depth=10. 2023-01-09 14:41:03 -06:00
David Harris
87e07e9081 Divider constant cleanup, made CORRSHIFTSZ consistent 2023-01-09 12:34:19 -08:00
Ross Thompson
8e618dd1b3 Added better branch predictor to fpga config. 2023-01-09 13:46:30 -06:00
Ross Thompson
685db5bb90 Fixed branch predictor. 2023-01-09 13:45:49 -06:00
Ross Thompson
e3df1d3326 Restored to default configuration. 2023-01-09 00:21:45 -06:00
Ross Thompson
f032eae7f5 Might have actually solved the gshare bug. 2023-01-09 00:11:25 -06:00
Ross Thompson
a35fb3addd core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
Ross Thompson
39731f99f4 Removed unused rv64BP config. 2023-01-07 12:17:40 -06:00
David Harris
31bffc305b Removed unused UARCH configuration entries 2023-01-06 05:11:14 -08:00
Ross Thompson
e34f80db2f More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
Ross Thompson
010168a69e Keep around the old gshare. 2023-01-05 15:55:46 -06:00
Ross Thompson
f3d871f2c3 Added speculative gshare. 2023-01-05 14:18:00 -06:00
Ross Thompson
3637067ace Officially added global history with speculation to types of branch predictors. 2023-01-05 14:04:09 -06:00
Ross Thompson
87c9682311 Simplified gshare. 2023-01-04 23:51:09 -06:00
Ross Thompson
f8c656f1e0 Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
David Harris
499b52a7f0 Handle special case Int Div/Rem of |A| < |B| in a single cycle 2023-01-01 13:54:01 -08:00
David Harris
dc27284b7f Broken commit starting to address radix 2 issues 2022-12-31 06:19:15 -08:00
David Harris
1e150160eb Moved shared config so wally-shared only has values a user would alter 2022-12-31 05:51:42 -08:00
David Harris
b2593e5cf5 config file, comment, postproc cleanup 2022-12-31 05:20:56 -08:00
Cedar Turek
5988ebb145 removed unnecessary values from shared config. unbroke division 2022-12-30 21:26:55 -08:00
Katherine Parry
668c698bb4 removed ethe second bit from fma alignment shift 2022-12-30 12:07:44 -06:00
Katherine Parry
8150305919 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-30 09:56:35 -06:00
David Harris
55f25457c9 Radix 4 divsqrt 2022-12-30 07:01:44 -08:00
Ross Thompson
a76ea1c6aa Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-29 17:07:53 -06:00
Ross Thompson
31ec70029e Re-enabled the branch predictor in rv64gc. 2022-12-29 17:07:50 -06:00
Katherine Parry
b469831b53 one bitt removed from inital lignment shift 2022-12-28 17:46:53 -06:00
Cedar Turek
6d933a88c7 idiv passing radix 2, four copies 2022-12-27 22:10:48 -08:00
Cedar Turek
d41b07aa85 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
David Harris
71f214df20 Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
cturek
04bc787647 Added negative-result int diviison support in U and UM registers. 13 tests pass! 2022-12-22 16:25:37 +00:00
David Harris
954051da13 Removed CSR support from rv32i 2022-12-19 16:15:12 -08:00
Alessandro Maiuolo
3bcb42adb6 fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8) 2022-12-18 19:04:36 -08:00
David Harris
3bef12b108 Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE 2022-12-15 08:23:34 -08:00
David Harris
e80e84aace Added IDIV_ON_FPU flag to control whether integer division uses FPU 2022-12-15 06:37:55 -08:00
Ross Thompson
fa22484cfe Reverted the IROM/DTIM address range modelsim assignment. 2022-11-30 17:13:33 -06:00
cturek
f10700e666 Added A<B signal to fdivsqrt, started postprocessing merge 2022-11-13 22:40:26 +00:00