cvw/pipelined/config
Ross Thompson dfd07a57fd Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
..
buildroot Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs 2022-08-26 21:29:26 -07:00
fpga Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs 2022-08-26 21:29:26 -07:00
rv32e Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
rv32gc Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
rv32i Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults. 2022-10-11 10:47:13 -05:00
rv32ic Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults. 2022-10-11 10:47:13 -05:00
rv64BP Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
rv64fpquad Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
rv64gc Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
rv64i Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults. 2022-10-11 10:47:13 -05:00
shared Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width 2022-10-10 09:10:55 -07:00