bbracker
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11cf251378
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-15 21:09:27 -04:00 |
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bbracker
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195cead01c
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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Domenico Ottolia
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b1cd107a00
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Add tests for scause and ucause
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2021-04-15 19:41:25 -04:00 |
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Domenico Ottolia
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a149f2f3d8
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Add support for vectored interrupts
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2021-04-15 19:13:42 -04:00 |
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Teo Ene
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a9c6d357d8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-15 15:29:09 -05:00 |
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Teo Ene
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7a40c27b59
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Quick fix to ahblite missing default statement done in class :)
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2021-04-15 15:29:04 -05:00 |
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Thomas Fleming
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e8770e3eac
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/mmu/priority_encoder.sv
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2021-04-15 16:20:43 -04:00 |
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Thomas Fleming
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e838f0bb3d
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Change priority encoder to avoid extra assignment
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2021-04-15 16:17:35 -04:00 |
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Thomas Fleming
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2c4682c4be
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Connect tlb and icache properly
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2021-04-15 14:48:39 -04:00 |
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Teo Ene
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cefc8ea22b
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Temporary change to mmu/priority_encoder.sv
Necessary to get synth working
Original HDL is still there, just commented out
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2021-04-15 13:37:12 -05:00 |
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Katherine Parry
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0bdd3efdd5
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integraded the FMA into the FPU
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2021-04-15 18:28:00 +00:00 |
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Ross Thompson
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534e3eaac8
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Merge branch 'bpfixes' into main
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2021-04-15 09:06:21 -05:00 |
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Shreya Sanghai
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75caa65df1
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Cherry Pick merge of Shreya's localhistory predictor changes into main.
fixed minor bugs in localHistory
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2021-04-15 09:04:36 -05:00 |
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ShreyaSanghai
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80fbd66113
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added localHistoryPredictor
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2021-04-15 08:58:22 -05:00 |
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Shreya Sanghai
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3696bf4f2c
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fixed bugs in global history to read latest GHRE
Cherry pick Shreya's commits into main branch.
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2021-04-15 08:55:22 -05:00 |
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bbracker
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76f50d7a69
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-15 09:06:03 -04:00 |
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bbracker
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da22308e60
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csri lint improvement
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2021-04-15 09:05:53 -04:00 |
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Thomas Fleming
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d281ecd067
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Remove imem from testbenches
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2021-04-14 20:20:34 -04:00 |
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bbracker
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ccff1e6c99
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rv64 interrupt servicing
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2021-04-14 10:19:42 -04:00 |
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Thomas Fleming
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bb2d433971
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Fix mmu lint errors
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2021-04-13 19:19:58 -04:00 |
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Thomas Fleming
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a545dcb9ae
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-13 17:15:10 -04:00 |
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Katherine Parry
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e075dc2d13
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Various bugs fixed in FMA
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2021-04-13 18:27:13 +00:00 |
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Thomas Fleming
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ae888b5705
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/pagetablewalker.sv
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2021-04-13 13:42:03 -04:00 |
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Thomas Fleming
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f0c926cf68
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Move InstrPageFault to fetch stage
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2021-04-13 13:39:22 -04:00 |
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Thomas Fleming
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08a84048b6
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Add lru algorithm to TLB
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2021-04-13 13:37:24 -04:00 |
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Teo Ene
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0bffac2c74
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Various code syntax changes to bring HDL to a synthesizable level
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2021-04-13 11:27:12 -05:00 |
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Ross Thompson
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cb52820249
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Fixed minor bug in muldiv which corrects the lint error.
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2021-04-09 10:56:31 -05:00 |
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Katherine Parry
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08f45eb076
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fixed FPU lint warnings
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2021-04-08 18:03:21 +00:00 |
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Katherine Parry
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ebf4915440
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fixed FPU lint warnings
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2021-04-08 17:55:25 +00:00 |
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Domenico Ottolia
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1bdfac6a77
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Cause an Illegal Instruction Exception when attempting to write readonly CSRs
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2021-04-08 05:12:54 -04:00 |
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Thomas Fleming
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bd310a55af
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Refactor TLB into multiple files
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2021-04-08 03:24:10 -04:00 |
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Thomas Fleming
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b3795cef2e
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Provide attribution link for priority encoder
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2021-04-08 03:05:06 -04:00 |
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Thomas Fleming
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e807f5d771
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Implement support for superpages
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2021-04-08 02:44:59 -04:00 |
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bbracker
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80a67dc906
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declare memread signal
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2021-04-05 08:13:01 -04:00 |
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bbracker
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eca92041e9
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PLIC claim reg side effects now check for memread signal
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2021-04-05 08:03:14 -04:00 |
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bbracker
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8f4da826fb
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plic subword access compliance
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2021-04-04 23:10:33 -04:00 |
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Katherine Parry
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f41b5a2d38
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Added missing files in FPU
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2021-04-04 18:09:13 +00:00 |
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bbracker
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ce7b2314ef
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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Thomas Fleming
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5946b860ca
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Comment out fpu from hart until module exists
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2021-04-03 22:34:11 -04:00 |
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Thomas Fleming
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8f31e00f6a
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Merge branch 'mmu' into main
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
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2021-04-03 22:12:52 -04:00 |
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Thomas Fleming
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ac89947e98
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-03 22:09:50 -04:00 |
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Thomas Fleming
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e04ad8f304
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Fix extraneous page fault stall
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2021-04-03 21:28:24 -04:00 |
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Katherine Parry
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08b31f7b2a
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Integrated FPU
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2021-04-03 20:52:26 +00:00 |
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Ross Thompson
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a743acd1fd
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Partial fix to the integer divide stall issue.
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2021-04-02 15:32:15 -05:00 |
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James E. Stine
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e38e7aff8e
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Minor cleanup
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2021-04-02 08:20:44 -05:00 |
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James E. Stine
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9026357350
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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Thomas Fleming
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14cf331265
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Merge branch 'main' into mmu
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2021-04-01 16:29:39 -04:00 |
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Thomas Fleming
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06032936bd
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-01 16:24:06 -04:00 |
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Thomas Fleming
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f9bf2fbc01
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Implement sfence.vma and fix tlb writing
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2021-04-01 15:55:05 -04:00 |
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James E. Stine
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59dee5580c
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Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.
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2021-04-01 12:30:37 -05:00 |
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