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891 Commits

Author SHA1 Message Date
Ross Thompson
8b9f30c91a more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
315f662eb9 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c Progress. 2022-08-30 14:17:00 -05:00
David Harris
e1760dde55 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
Ross Thompson
8cf3c7b352 new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00
Ross Thompson
a2220fc142 Have a rough working multi manager! 2022-08-29 17:11:27 -05:00
Ross Thompson
f5584bb41c Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu. 2022-08-29 17:04:53 -05:00
David Harris
28db4fdc70 commented out lines to have divider work again 2022-08-29 13:01:32 -07:00
David Harris
87b77658f2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 12:01:13 -07:00
David Harris
a6efbb3fda Initial FDIVSQRT simplification working 2022-08-29 12:01:09 -07:00
Ross Thompson
233777f744 Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager. 2022-08-29 13:01:24 -05:00
Ross Thompson
e805f33f4e Typo. 2022-08-29 11:40:35 -05:00
Ross Thompson
dceaf6e4e3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 11:38:37 -05:00
Ross Thompson
e7de0e033e Added comments about planned changes. 2022-08-29 09:48:00 -05:00
David Harris
a82cf3d0ba Simplify FSM 2022-08-29 04:32:27 -07:00
David Harris
7856f08e1d Renamed special case 2022-08-29 04:29:58 -07:00
David Harris
7d4e85bf21 Separated out radix 2 and radix 4 stages into different modules 2022-08-29 04:26:14 -07:00
David Harris
2788022c22 renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
Ross Thompson
7b76fbaa9a Removed ignore request from busfsm. 2022-08-28 21:12:27 -05:00
Ross Thompson
122c88ee46 Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
Ross Thompson
5e63af5887 Reordered the adrdecs. 2022-08-28 13:38:57 -05:00
Ross Thompson
dd7736cb93 Possible fix. 2022-08-28 13:10:47 -05:00
Ross Thompson
a81fcc6b4b Partial fix to bus + dtim. 2022-08-27 23:44:17 -05:00
David Harris
f2517f8290 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
David Harris
60b673cafd Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus 2022-08-27 05:31:56 -07:00
David Harris
37f0b52520 Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00
David Harris
2b241f8bbd Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
David Harris
03e731b3ff Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
f0b4f69b65 Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
David Harris
812158aeee Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
95dd50a567 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
David Harris
ca6837f597 Fixed endian swapping on bus only 2022-08-26 19:58:04 -07:00
David Harris
5f37e16b62 Fixed rv32e LSU and IFU issues 2022-08-25 20:02:38 -07:00
David Harris
671ea60f3e lsu simplification 2022-08-25 18:52:42 -07:00
David Harris
ec2c6d4fcb busfsm simplified 2022-08-25 18:36:53 -07:00
David Harris
f262abb5c3 Removed unused signals 2022-08-25 18:34:39 -07:00
David Harris
b73286ece6 Removed unused signals 2022-08-25 18:30:46 -07:00
David Harris
949e76bc83 Removed UncachedBusRead and UncachedBusWrite 2022-08-25 18:24:39 -07:00
David Harris
e39694694c Restored ahbtranstype 2022-08-25 18:22:26 -07:00
David Harris
83d3782f2c Removed ahbtranstype 2022-08-25 18:21:45 -07:00
David Harris
543fbd1fa9 Removed WordCountFlag 2022-08-25 18:21:18 -07:00
David Harris
d118fcbde8 Removed UncachedAccess 2022-08-25 18:20:52 -07:00
David Harris
bac95823b6 Removed UncachedRW 2022-08-25 18:19:41 -07:00
David Harris
cfcde754c3 Removed CacheBusAck 2022-08-25 18:17:34 -07:00
David Harris
9bc62ce124 Removed SelUncachedAdr 2022-08-25 18:15:59 -07:00
David Harris
f39e62eeea Removed Cache_Enabled 2022-08-25 18:13:34 -07:00
David Harris
5bfaf31df0 Removed STATE_BUS_FETCH and STATE_BUS_WRITE 2022-08-25 18:12:09 -07:00
David Harris
85e93e2bb7 Removed CacheFetchLine and CacheWriteLine 2022-08-25 18:10:15 -07:00
David Harris
23a102b1b9 Removed CountEn 2022-08-25 18:05:44 -07:00
David Harris
e485e986a5 Removed wordcount 2022-08-25 18:04:49 -07:00
David Harris
69dff87feb Added buscachefsm for system with bus and cache 2022-08-25 18:01:01 -07:00
David Harris
5340c45dfc Separated busdp for cache from simpler logic for no cache 2022-08-25 17:54:04 -07:00
David Harris
9a92bfe095 Simplified swbytemask 2022-08-25 17:32:16 -07:00
David Harris
eb753b3b3f FIxed wallypipelinedsoc merge conflict 2022-08-25 15:36:47 -07:00
David Harris
902d2067ba Removed delayed AHB signals from top level 2022-08-25 15:34:14 -07:00
Ross Thompson
db635e3ad2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
Ross Thompson
8c8b95ecf5 Finally resolved the issues with the rv32ic and rv64ic configurations. 2022-08-25 16:00:55 -05:00
Ross Thompson
5c2bc20dbd Almost fixed issues with irom and dtim address selection. 2022-08-25 15:52:25 -05:00
David Harris
302a7fa294 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
179aec3616 Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
David Harris
07225cabb7 Fixed brom name 2022-08-25 12:48:00 -07:00
Ross Thompson
d23888407b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:45:02 -05:00
David Harris
1226b2889e ahblite cleanup 2022-08-25 12:44:25 -07:00
Ross Thompson
f67010c688 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:40:52 -05:00
David Harris
bc0c7d0cd8 Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
David Harris
c442dea173 Removed M sufix from busdp signals 2022-08-25 11:13:01 -07:00
David Harris
48f346baf8 Renamed LSUFunct3M to Funct3 in busdp 2022-08-25 11:08:12 -07:00
David Harris
9bada9c14a Renaming LSU signals from busdp 2022-08-25 11:05:10 -07:00
David Harris
3ba961d1a8 renamed BusBuffer to FetchBuffer 2022-08-25 10:44:39 -07:00
David Harris
dda3b441d7 Continued busdp/ebu simplification 2022-08-25 10:20:02 -07:00
David Harris
19fe6d106c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:52:49 -07:00
David Harris
aba914ea5e Renamed AHB signals coming out of LSU to LSH_<AHBNAME> 2022-08-25 09:52:08 -07:00
Ross Thompson
e605ef57dc BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
b0aea77b20 Added generate around uncore. 2022-08-25 10:35:24 -05:00
Ross Thompson
01a7718471 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
ad485fe591 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:03:34 -05:00
Ross Thompson
701324eeb8 Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
David Harris
ae0702d129 Renamed DCache to Cache in busdp/busfsm signal interface 2022-08-25 06:21:22 -07:00
David Harris
3500286803 Cleanup typos 2022-08-25 04:32:19 -07:00
David Harris
db5c941d6f Minor name cleanups 2022-08-25 04:28:25 -07:00
David Harris
1206b388c7 Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM 2022-08-25 04:06:27 -07:00
David Harris
f7209627c2 removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
David Harris
562be633ab Stripped write capaibilty out of rom_ahb 2022-08-24 17:23:08 -07:00
David Harris
a131e1f17a Added ROM module and moved memories into generic/mem 2022-08-24 17:03:22 -07:00
David Harris
6785644fb8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-24 16:30:28 -07:00
David Harris
b21b91234b Ram cleanup 2022-08-24 16:30:25 -07:00
Ross Thompson
769af32f2a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
fc22e807e2 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
d23b309e0d Fixed lint errors with bram wrapper. 2022-08-24 13:19:23 -05:00
Ross Thompson
51adf6cba9 Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
bcb52acfba bram synthesis test 2022-08-23 19:34:45 -07:00
Ross Thompson
e4cbb43c67 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 18:52:15 -05:00
Ross Thompson
642dc170d7 Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite. 2022-08-23 18:51:11 -05:00
David Harris
5eebd521c5 Fixed FPU-IEU forwarding stall 2022-08-23 14:14:41 -07:00
David Harris
d72068d582 Only stall FPU to IEU on convert instructions with dependencies 2022-08-23 12:57:18 -07:00
David Harris
05aa18fe14 Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
David Harris
d19fc99bf0 Simplify IEU-FP datapath 2022-08-23 11:16:36 -07:00
David Harris
f72d07adce Improved illegal instruction checking in FPU 2022-08-23 11:08:02 -07:00
David Harris
c61dba6192 Fixed LSU typos 2022-08-23 10:23:08 -07:00
David Harris
2a1bd53663 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 10:14:59 -07:00