cvw/pipelined/src
2022-08-25 18:36:53 -07:00
..
cache Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
ebu Separated busdp for cache from simpler logic for no cache 2022-08-25 17:54:04 -07:00
fpu Only stall FPU to IEU on convert instructions with dependencies 2022-08-23 12:57:18 -07:00
generic Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:52:49 -07:00
hazard Simplified FPU-LSU interface to skip IEU 2022-08-22 13:28:51 -07:00
ieu Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
ifu Finally resolved the issues with the rv32ic and rv64ic configurations. 2022-08-25 16:00:55 -05:00
lsu busfsm simplified 2022-08-25 18:36:53 -07:00
mmu Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
uncore Removed delayed AHB signals from top level 2022-08-25 15:34:14 -07:00
wally FIxed wallypipelinedsoc merge conflict 2022-08-25 15:36:47 -07:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00