Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-24 05:24:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
8,916 Commits 4 Branches 2 Tags 52 MiB
04cd2c8ea4
Commit Graph

229 Commits

Author SHA1 Message Date
Ross Thompson
ab1ee3d69b Removed *** from IFU, lrcs. 2024-06-19 09:40:35 -07:00
Ross Thompson
c5dac4d775 Removed *** from fpga top. 2024-06-19 09:28:21 -07:00
Jacob Pease
7a417d7a6c Added true bootloader to fpga/zsbl directory. 2024-05-31 15:28:25 -05:00
Jacob Pease
3f7659c8ad Removed old fpgaTop.v file. 2024-05-30 16:15:19 -05:00
Jacob Pease
7ecd1c7d5f The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
Rose Thompson
8123695831 Maded insert_debug_comment.sh compatible with cygwin. 2024-04-22 10:48:34 -05:00
Rose Thompson
3bed733301 Fixed fpga to work with the updated regression changes. 2024-04-22 10:42:01 -05:00
Rose Thompson
c1221e6608 Fixed insert_debug_comment.sh to work with the older version of bash. 2024-04-16 10:55:26 -05:00
Rose Thompson
6097444b5a Added missing file for compiling the fpga zero stage bootloader. 2024-04-11 10:30:56 -05:00
Rose Thompson
60f96112db Moved the zero stage boot loader to the fpga directory. 2024-03-01 10:23:55 -06:00
Rose Thompson
cc7f433ce0 Update the fpga scripts to use the new derivative configs. 2024-01-31 13:19:28 -06:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
7693c5d4e2 Updates to fpga top level. 2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388 Replaced fpga's verilog top with system verilog. 2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c Replaced fpga top level verilog with system verilog. 2023-12-15 13:07:08 -06:00
Rose Thompson
34631c54d3 Get's the fpga building again after the git history rewrite. 2023-12-14 17:08:25 -06:00
Jacob Pease
7e494f2d3b Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile. 2023-12-01 18:59:18 -06:00
Jacob Pease
71066cae12 Modified FPGA Makefile to override with relative path. FPGA boots now. 2023-11-30 17:51:15 -06:00
Rose Thompson
b137759b45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-20 10:34:36 -06:00
Rose Thompson
cdd21d6635 Added menvcfg to debugger for checking what linux has configured. 2023-11-19 13:44:22 -06:00
Jacob Pease
87e6a5ccf2 Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. 2023-11-18 19:15:39 -06:00
Jacob Pease
ff73f798ed Replaced vivado-risc-v addins directory with new SDC repo. 2023-11-16 13:59:12 -06:00
Rose Thompson
d4bc9da085 Fixed another bug in the updated script changes. 2023-11-13 18:12:02 -06:00
Rose Thompson
f8b65f50b0 Fixed bugs in the updated fpga synthe script. 2023-11-13 18:10:22 -06:00
Rose Thompson
d5f0c15b90 Modified the fpga build script to generate it's own config file rather than use the one in config/fpga. 2023-11-13 17:48:28 -06:00
Rose Thompson
6b7ff50a84 Reduced Arty A7 clock speed to 20Mhz to support Zicclsm. 2023-11-13 16:44:02 -06:00
Ross Thompson
d33c966a42 Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock. 2023-10-10 17:46:12 -05:00
Ross Thompson
055e00b8ac Pushed vcu118 to 71MHz. 2023-08-25 17:04:50 -05:00
Jacob Pease
2bf6207919 Added help option to the flash-sd script. 2023-08-22 13:37:33 -05:00
Jacob Pease
e489ede51d Merge branch 'main' of github.com:openhwgroup/cvw 2023-08-21 16:10:09 -05:00
David Harris
d801916d97 Merge pull request #383 from ross144/main 
Adds Zicbom support for D-cache only.  I-cache not yet supported.  Tests 32 and 64 bit versions.  Please rebuild regressions wally32 and wally64.  To save rebuild time edit lines 11-12 of tests/riscof/Makefile
 2023-08-21 13:32:00 -07:00
Ross Thompson
a16cde3dc6 Removed unused file. 2023-08-21 15:12:59 -05:00
Ross Thompson
1e0f1aeeac Updated artyA7 debugger to match book. 2023-08-21 14:35:42 -05:00
Jacob Pease
144d93eba4 Added SPDX headers to other probe scripts. 2023-08-16 14:04:25 -05:00
Jacob Pease
f91157fc95 Added SPDX header to probe script. 2023-08-16 13:05:37 -05:00
Jacob Pease
c2f2bef433 Fixed bug caused by errant tab size in probe script. 2023-08-16 12:20:08 -05:00
Jacob Pease
63e901e981 Added probe script to generate a single probe for the fpga. 2023-08-16 12:12:31 -05:00
Ross Thompson
cab40e618f Updateds to vcu118 constraints and device tree. 2023-08-02 16:51:32 -05:00
Ross Thompson
fb1c1a1832 Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails. 2023-08-02 16:14:04 -05:00
Ross Thompson
5790dafdce Fixed constraint in VCU118. 2023-08-02 13:02:28 -05:00
Ross Thompson
c4ae856f92 Clean up vcu118 synth scripts. 2023-08-01 14:39:33 -05:00
Ross Thompson
06efd2cdde Pushed performance of arty a7 to 23Mhz. 2023-07-31 14:13:09 -05:00
Jacob Pease
9d33e08dbb Removed non-existent SDC dependency from VCU targets in FPGA Makefile. 2023-07-27 15:01:20 -05:00
Jacob Pease
b626f2185a Fixed GPIO pin names in fpgaTop.v 2023-07-25 20:57:04 -05:00
Ross Thompson
b1f7a5768f Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
49b87d4550 Merge branch 'main' of github.com:ross144/cvw 2023-07-24 10:47:05 -05:00
Ross Thompson
065e5e98c9 Improved timing constraints for arty a7 to push clock speed to 20Mhz. 2023-07-24 10:46:49 -05:00
Ross Thompson
63afd95ad3 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
ab6ef5bb58 At least it simulates and gets through fpga elaboration. 2023-07-21 18:40:26 -05:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00