cturek
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04ac350a29
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Added flops to preproc
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2022-12-02 20:31:08 +00:00 |
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David Harris
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3a07d56d33
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Renamed FPUStallD to FCvtIntStallD
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2022-12-02 11:55:23 -08:00 |
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David Harris
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1b0f878c16
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Renamed DivStartE to IFDivStartE
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2022-12-02 11:30:49 -08:00 |
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David Harris
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db5f3c15a4
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FPU divider working with execute stage stall
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2022-12-02 11:11:53 -08:00 |
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Ross Thompson
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3442b04f9e
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Properly flush cacheLRU.
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2022-12-01 17:32:58 -06:00 |
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Ross Thompson
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e403800ce8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 11:47:54 -06:00 |
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Ross Thompson
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5025664cb0
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Removed unused port on cacheway.
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2022-12-01 11:47:48 -06:00 |
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David Harris
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28996d0b12
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 08:15:51 -08:00 |
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David Harris
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1bd639be6d
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code cleanup
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2022-12-01 08:15:48 -08:00 |
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Ross Thompson
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e6bd86f4fa
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 17:19:04 -06:00 |
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David Harris
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4ddc8fd603
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signal sufixes in integer division
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2022-11-30 15:15:37 -08:00 |
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Ross Thompson
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a6355b1dcb
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More optimization.
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2022-11-30 11:26:48 -06:00 |
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Ross Thompson
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0aa7ce0b24
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Removed reset on dirty cache bits.
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2022-11-30 11:04:37 -06:00 |
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Ross Thompson
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cedb234013
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Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
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2022-11-30 11:01:25 -06:00 |
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Ross Thompson
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0454eb95ad
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Preparing to merge dirty and tag srams.
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2022-11-30 10:40:48 -06:00 |
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Ross Thompson
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de538d1c2f
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Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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Ross Thompson
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453ea36512
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Optimization of cacheway.
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2022-11-29 18:30:47 -06:00 |
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Ross Thompson
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fbf543bf57
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Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
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2022-11-29 17:19:31 -06:00 |
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Ross Thompson
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b5718c9baa
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Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
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2022-11-29 14:51:09 -06:00 |
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Ross Thompson
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96cc4c7ebe
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Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
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2022-11-29 14:09:48 -06:00 |
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Ross Thompson
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78acd40424
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Renamed signals in the cache.
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2022-11-29 10:52:40 -06:00 |
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Ross Thompson
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6dd5668d21
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-22 18:07:32 -06:00 |
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cturek
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bdb9e24a66
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Almost done with Int division
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2022-11-22 22:22:59 +00:00 |
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Ross Thompson
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279f5bc615
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Cleanup cacheLRU.
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2022-11-22 14:59:01 -06:00 |
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Ross Thompson
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e1dbe58632
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File name change for cachereplacement policy to cacheLRU
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2022-11-20 22:35:02 -06:00 |
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Ross Thompson
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4e926ba4cf
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Signal name changes for LRU.
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2022-11-20 22:31:36 -06:00 |
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Ross Thompson
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00218d559f
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Missing a file. Last commit will fail.
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2022-11-17 17:45:41 -06:00 |
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Ross Thompson
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0106777f02
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Finally have the correct replacement policy implementation.
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2022-11-17 17:36:37 -06:00 |
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Ross Thompson
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faa13a96e0
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I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
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2022-11-16 15:38:37 -06:00 |
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Ross Thompson
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22ad49eef2
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Progress on the cache replacement policy implementation.
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2022-11-16 15:35:34 -06:00 |
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Ross Thompson
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0796cd92fc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-16 12:42:29 -06:00 |
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Ross Thompson
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42111db671
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Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
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2022-11-16 12:36:58 -06:00 |
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David Harris
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59335ac70f
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comment cleanup
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2022-11-16 10:23:20 -08:00 |
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David Harris
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be9c618c94
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Renamed DivBusy to FDivBusyE in FPU
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2022-11-16 10:13:27 -08:00 |
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David Harris
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128cc86254
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Moved DivStartE to fdivsqrtfsm
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2022-11-16 10:00:07 -08:00 |
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Ross Thompson
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1f21a2bab1
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Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
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2022-11-16 11:15:34 -06:00 |
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cturek
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ffd03e9548
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Attempt to fix FPGA synth errors
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2022-11-15 20:34:28 +00:00 |
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cturek
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98b66aab9f
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Fixed lint errors in postprocessing
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2022-11-15 20:31:23 +00:00 |
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Ross Thompson
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3df51716b1
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Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
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2022-11-14 16:02:20 -06:00 |
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Ross Thompson
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b53f8eceef
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Renamed Flush to FlushStage in the cache.
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2022-11-14 14:11:05 -06:00 |
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Ross Thompson
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284b97aff6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-14 13:48:56 -06:00 |
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David Harris
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6372139af4
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Removed comment about nonexistent possible bug
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2022-11-14 09:56:33 -08:00 |
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David Harris
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06dbed92c8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-14 09:52:24 -08:00 |
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David Harris
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f9202187ba
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Removed comment about nonexistent possible bug
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2022-11-14 09:52:21 -08:00 |
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Ross Thompson
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13e6f7d80b
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Changed names of cache signals.
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2022-11-13 21:36:12 -06:00 |
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cturek
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abaa33b92a
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Added majority of combinational logic
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2022-11-14 00:06:38 +00:00 |
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cturek
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6740d77b63
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Added Quotient/Remainder calcs to normal termination
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2022-11-13 23:44:34 +00:00 |
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cturek
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12e3646153
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Added flops for n and m, added B=0 signal
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2022-11-13 23:02:43 +00:00 |
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cturek
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f10700e666
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Added A<B signal to fdivsqrt, started postprocessing merge
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2022-11-13 22:40:26 +00:00 |
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Ross Thompson
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9d7ba19fe1
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Changed IMWriteDataM to IHWriteDataM.
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2022-11-13 12:27:48 -06:00 |
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