David Harris
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824bc0dab7
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Fixed expected value on WALLY-satp-invalid
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2024-02-16 11:12:57 -08:00 |
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Rose Thompson
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6110799a1e
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Updated the wally rv32 priv tests to not use sail.
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2024-02-16 11:39:06 -06:00 |
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David Harris
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b362320dd9
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Removed unused Makefiles and Makefrags from wally-riscv-arch-test now that it is only used by riscof
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2024-02-16 06:46:49 -08:00 |
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David Harris
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d094201362
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Added NO_SAIL to wally-riscv-arch-test cases that stopped passing in Sail
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2024-02-16 06:27:49 -08:00 |
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David Harris
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d9003da8e0
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Moved some tests to wally-riscv-arch-test list that are simulated
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2024-01-30 10:28:51 -08:00 |
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naichewa
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8b60992e72
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fixed SPI tests failing when no icache
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2024-01-17 14:38:11 -08:00 |
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Rose Thompson
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0b2af0c99a
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Modifed the sv39 tests so they work with just 128MiB physical memory.
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2024-01-12 20:00:21 -06:00 |
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Rose Thompson
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e6a2595936
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Modified sv48 svadu test to work with 128MB rather than 2GB physical memory.
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2024-01-12 11:05:06 -06:00 |
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David Harris
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caedab679a
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Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
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2024-01-07 07:14:12 -08:00 |
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David Harris
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0ff049db86
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Removed unused tests from wally-riscv-arch-test
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2023-12-20 13:34:12 -08:00 |
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David Harris
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8552369687
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Merged PR538, delete unused tests
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2023-12-20 13:30:31 -08:00 |
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Rose Thompson
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70d0169019
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All regression tests which matter are running!
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2023-12-20 14:57:52 -06:00 |
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Rose Thompson
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1b59182d59
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Updated tests with ending label.
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2023-12-20 14:55:37 -06:00 |
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Rose Thompson
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49b1b7c7f9
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Fixed the last uninitialized memory issue in the priv tests.
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2023-12-19 16:51:56 -06:00 |
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Rose Thompson
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b04ad23c33
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Fixed bugs in the wally64periph signature.
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2023-12-19 16:16:59 -06:00 |
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Rose Thompson
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726efee1e2
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Fixed bugs in the cbom test.
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2023-12-19 15:53:48 -06:00 |
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Rose Thompson
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418ae0decc
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Fixed some regression tests with David's help.
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2023-12-19 14:18:21 -06:00 |
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David Harris
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a138ef37b1
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Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)
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2023-12-15 19:26:50 -08:00 |
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David Harris
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29f57958a9
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Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match
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2023-12-14 15:32:36 -08:00 |
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David Harris
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166c98b6f6
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Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn
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2023-12-13 19:43:17 -08:00 |
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David Harris
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6c017141c5
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Renamed HADE to ADUE for Svadu
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2023-12-13 11:49:04 -08:00 |
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Rose Thompson
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9dfe421c55
|
Yay! Zicclsm passes my regression test now.
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2023-11-10 18:28:51 -06:00 |
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Rose Thompson
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c0e02ae190
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Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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02ab9fe99c
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Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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bd866e1025
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Fixed some more bugs in the Zicclsm signature.
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2023-11-10 17:36:10 -06:00 |
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Rose Thompson
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efecb0c346
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Fixed bug in the Zicclsm test.
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2023-11-10 17:34:23 -06:00 |
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Rose Thompson
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ada354f443
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Fixed bug in the misaligned access test.
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2023-11-10 17:02:15 -06:00 |
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Rose Thompson
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b74bfbeefd
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
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naichewa
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d67badfc60
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fix hardware interlock, hold mode deassert
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2023-11-08 15:20:51 -08:00 |
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naichewa
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a5837eb62c
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
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naichewa
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4651b807ed
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added test cases
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2023-11-02 15:43:08 -07:00 |
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Rose Thompson
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0a4ed5515b
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Merge branch 'main' into Zicclsm
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2023-11-02 12:55:51 -05:00 |
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Rose Thompson
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afa1d85e3b
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Doesn't yet fully work.
Thomas is going to finish debugging while I'm on the RISCV summit next week.
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2023-11-02 12:07:42 -05:00 |
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Rose Thompson
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7ba891f607
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Progress. I think the remaining bugs are in the regression test's signature.
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2023-11-01 17:51:48 -05:00 |
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naichewa
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9aa8a7af3e
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comments, more test cases
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2023-11-01 01:26:34 -07:00 |
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Rose Thompson
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5660eff57d
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Working through issues with the psill logic.
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2023-10-31 18:50:13 -05:00 |
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Rose Thompson
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4984b3935f
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Progress
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2023-10-31 14:50:33 -05:00 |
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Rose Thompson
|
5ca428d6a8
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Fixed bugs in misaligned test.
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2023-10-31 12:49:35 -05:00 |
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Rose Thompson
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c061440141
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First stab at the misaligned test.
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2023-10-31 12:30:10 -05:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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2330f4ee63
|
hardware interlock
|
2023-10-30 17:00:20 -07:00 |
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Rose Thompson
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2241976d29
|
Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
|
2023-10-30 18:26:11 -05:00 |
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David Harris
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f6a7f707bd
|
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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Rose Thompson
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0fd5b3b2ce
|
Updated comments in the cboz tests.
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2023-10-20 15:15:47 -05:00 |
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Rose Thompson
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5a4028064a
|
Updated comments for the cbom tests.
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2023-10-20 15:13:52 -05:00 |
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naichewa
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0ff9ce527d
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Merge branch 'main' into spi
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2023-10-16 22:59:50 -07:00 |
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David Harris
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ac4216b43d
|
Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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David Harris
|
6245748ed7
|
Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
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2023-10-15 15:31:03 -07:00 |
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David Harris
|
b4891d88db
|
Added WALLY minfo test for rv32
|
2023-10-15 06:48:22 -07:00 |
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David Harris
|
434d6b2c5c
|
minfo test working again with mconfigptr for RV64
|
2023-10-15 06:41:52 -07:00 |
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