Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-24 13:34:28 +00:00
Code Issues Packages Projects Releases Wiki Activity
26cd22c388
cvw/fpga/generator/Makefile

92 lines
4.0 KiB
Makefile
Raw Normal View History

Created Makefile to manage IP generation.
2021-11-30 00:32:51 +00:00
dst := IP
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 16:08:35 +00:00
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 20:38:39 +00:00
# vcu118
Wow. The newest version of Vivado does not like the enums as parameters. The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 20:07:10 +00:00
#export XILINX_PART := xcvu9p-flga2104-2L-e
#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
#export board := vcu118
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 20:38:39 +00:00
# vcu108
Get's the fpga building again after the git history rewrite.
2023-12-14 23:08:25 +00:00
#export XILINX_PART := xcvu095-ffva2104-2-e
#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
#export board := vcu108
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 20:38:39 +00:00
Updated to help debut Jacob's crossbar woes.
2023-04-11 19:22:42 +00:00
# Arty A7
Get's the fpga building again after the git history rewrite.
2023-12-14 23:08:25 +00:00
export XILINX_PART := xc7a100tcsg324-1
export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
export board := ArtyA7
Created Makefile to manage IP generation.
2021-11-30 00:32:51 +00:00
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 16:08:35 +00:00
# for Arty A7 and S7 boards
Get's the fpga building again after the git history rewrite.
2023-12-14 23:08:25 +00:00
all: FPGA_Arty
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 16:08:35 +00:00
# VCU 108 and VCU 118 boards
Fixed bugs in the updated fpga synthe script.
2023-11-14 00:10:22 +00:00
#all: FPGA_VCU
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 16:08:35 +00:00
At least it simulates and gets through fpga elaboration.
2023-07-21 23:35:27 +00:00
FPGA_Arty: PreProcessFiles IP_Arty
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 16:08:35 +00:00
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
Created Makefile to manage IP generation.
2021-11-30 00:32:51 +00:00
Removed non-existent SDC dependency from VCU targets in FPGA Makefile.
2023-07-27 20:01:20 +00:00
FPGA_VCU: PreProcessFiles IP_VCU
Fixed bug with fpga makefile.
2022-11-07 15:20:05 +00:00
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
Improved FPGA makefile and fixed timing constraints in clock converter.
2021-12-03 16:05:13 +00:00
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 16:08:35 +00:00
IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 20:38:39 +00:00
$(dst)/xlnx_ddr4-$(board).log \
Updated to help debut Jacob's crossbar woes.
2023-04-11 19:22:42 +00:00
$(dst)/xlnx_axi_clock_converter.log \
Connected the axi_sdc_controller with an axi crossbar. Added an adrdec.sv to the adrdecs.sv file for the sake of the cache. Modified Uncore accordingly.
2023-01-13 19:56:01 +00:00
$(dst)/xlnx_ahblite_axi_bridge.log \
$(dst)/xlnx_axi_crossbar.log \
$(dst)/xlnx_axi_dwidth_conv_32to64.log \
Modified makefile. Added axi protocol converter IP.
2023-01-24 01:30:29 +00:00
$(dst)/xlnx_axi_dwidth_conv_64to32.log \
$(dst)/xlnx_axi_prtcl_conv.log
Updated to help debut Jacob's crossbar woes.
2023-04-11 19:22:42 +00:00
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 16:08:35 +00:00
IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
$(dst)/xlnx_ddr3-$(board).log \
Fixed more issues with arty a7 constarints.
2023-04-16 18:25:02 +00:00
$(dst)/xlnx_mmcm.log \
Created Makefile to manage IP generation.
2021-11-30 00:32:51 +00:00
$(dst)/xlnx_axi_clock_converter.log \
At least it simulates and gets through fpga elaboration.
2023-07-21 23:35:27 +00:00
$(dst)/xlnx_ahblite_axi_bridge.log \
Merge branch 'boot' into mergeBoot Merges Jacob's new sdc controller into wally.
2023-07-21 22:43:45 +00:00
$(dst)/xlnx_axi_crossbar.log \
$(dst)/xlnx_axi_dwidth_conv_32to64.log \
$(dst)/xlnx_axi_dwidth_conv_64to32.log \
$(dst)/xlnx_axi_prtcl_conv.log
Created Makefile to manage IP generation.
2021-11-30 00:32:51 +00:00
Removed SDC from repo due to copy right issue. Modified fpga build flow to reference it outside the repo.
2023-01-20 20:35:46 +00:00
Removed mark_debug vivado directive from source code. Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory.
2023-01-21 01:43:18 +00:00
PreProcessFiles:
Updated fpga constraints.
2023-01-21 02:16:33 +00:00
rm -rf ../src/CopiedFiles_do_not_add_to_repo/
Removed pipelined level of hierarchy
2023-02-02 22:14:11 +00:00
cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
2023-11-13 23:48:28 +00:00
mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
Fixed another bug in the updated script changes.
2023-11-14 00:12:02 +00:00
cp ../../config/rv64gc/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
Removed mark_debug vivado directive from source code. Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory.
2023-01-21 01:43:18 +00:00
./insert_debug_comment.sh
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
2023-11-13 23:48:28 +00:00
# modify config *** RT: eventually setup for variably defined sized memory
Get's the fpga building again after the git history rewrite.
2023-12-14 23:08:25 +00:00
sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
2023-11-13 23:48:28 +00:00
sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 64'h00000FFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UNCORE_RAM_PRELOAD.*/UNCORE_RAM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/EXT_MEM_SUPPORTED.*/EXT_MEM_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/SDC_SUPPORTED.*/SDC_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
Fixed bugs in the updated fpga synthe script.
2023-11-14 00:10:22 +00:00
sed -i "s/SPI_SUPPORTED.*/SPI_SUPPORTED = 1'b0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # *** RT: Add SPI when ready
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
2023-11-13 23:48:28 +00:00
sed -i "s/GPIO_LOOPBACK_TEST.*/GPIO_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/SPI_LOOPBACK_TEST.*/SPI_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UART_PRESCALE.*/UART_PRESCALE = 32'd0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
Fixed bugs in the updated fpga synthe script.
2023-11-14 00:10:22 +00:00
sed -i "s/PLIC_NUM_SRC = .*/PLIC_NUM_SRC = 32'd53;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
2023-11-13 23:48:28 +00:00
sed -i "s/PLIC_SDC_ID.*/PLIC_SDC_ID = 32'd20;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/BPRED_SIZE.*/BPRED_SIZE = 32'd12;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
Modified FPGA Makefile to override with relative path. FPGA boots now.
2023-11-30 23:51:15 +00:00
sed -i "s/$\$readmemh.*/$\$readmemh(\"..\/..\/..\/fpga\/src\/boot.mem\", ROM, 0);/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.
2023-12-02 00:59:18 +00:00
# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
Removed mark_debug vivado directive from source code. Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory.
2023-01-21 01:43:18 +00:00
Created Makefile to manage IP generation.
2021-11-30 00:32:51 +00:00
$(dst)/%.log: %.tcl
mkdir -p IP
cd IP;\
vivado -mode batch -source ../$*.tcl | tee $*.log
Added make clean to fpga IP generator.
2021-11-30 00:42:28 +00:00
Improved FPGA makefile and fixed timing constraints in clock converter.
2021-12-03 16:05:13 +00:00
cleanIP:
rm -rf IP
cleanLogs:
rm -rf *.jou *.log
cleanFPGA:
rm -rf WallyFPGA.* reports sim .Xil
cleanAll: cleanIP cleanLogs cleanFPGA
Reference in New Issue Copy Permalink