cvw/fpga/generator/Makefile

dst := IP

# vcu118
#export XILINX_PART := xcvu9p-flga2104-2L-e
#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
#export board := vcu118

# vcu108
#export XILINX_PART := xcvu095-ffva2104-2-e
#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
#export board := vcu108

# Arty A7
export XILINX_PART := xc7a100tcsg324-1
export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
export board := ArtyA7

# for Arty A7 and S7 boards
all: FPGA_Arty

# VCU 108 and VCU 118 boards
#all: FPGA_VCU

FPGA_Arty: PreProcessFiles IP_Arty
	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log

FPGA_VCU: PreProcessFiles IP_VCU SDC
	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log

IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
	$(dst)/xlnx_ddr4-$(board).log \
	$(dst)/xlnx_axi_clock_converter.log \
	$(dst)/xlnx_ahblite_axi_bridge.log \
	$(dst)/xlnx_axi_crossbar.log \
	$(dst)/xlnx_axi_dwidth_conv_32to64.log \
	$(dst)/xlnx_axi_dwidth_conv_64to32.log \
	$(dst)/xlnx_axi_prtcl_conv.log

IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
	$(dst)/xlnx_ddr3-$(board).log \
	$(dst)/xlnx_mmcm.log \
	$(dst)/xlnx_axi_clock_converter.log \
	$(dst)/xlnx_ahblite_axi_bridge.log \
	$(dst)/xlnx_axi_crossbar.log \
	$(dst)/xlnx_axi_dwidth_conv_32to64.log \
	$(dst)/xlnx_axi_dwidth_conv_64to32.log \
	$(dst)/xlnx_axi_prtcl_conv.log


PreProcessFiles:
	rm -rf ../src/CopiedFiles_do_not_add_to_repo/
	cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
	./insert_debug_comment.sh

$(dst)/%.log: %.tcl
	mkdir -p IP
	cd IP;\
	vivado -mode batch -source ../$*.tcl | tee $*.log

cleanIP:
	rm -rf IP

cleanLogs:
	rm -rf  *.jou *.log

cleanFPGA:
	rm -rf WallyFPGA.* reports sim .Xil

cleanAll: cleanIP cleanLogs cleanFPGA
Created Makefile to manage IP generation. 2021-11-30 00:32:51 +00:00			`dst := IP`
Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 16:08:35 +00:00
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 20:38:39 +00:00			`# vcu118`
Wow. The newest version of Vivado does not like the enums as parameters. The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers. 2023-07-18 20:07:10 +00:00			`#export XILINX_PART := xcvu9p-flga2104-2L-e`
			`#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4`
			`#export board := vcu118`
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 20:38:39 +00:00
			`# vcu108`
Finally building ddr3 xilinx ip from script. 2023-04-10 19:36:33 +00:00			`#export XILINX_PART := xcvu095-ffva2104-2-e`
			`#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2`
			`#export board := vcu108`
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 20:38:39 +00:00
Updated to help debut Jacob's crossbar woes. 2023-04-11 19:22:42 +00:00			`# Arty A7`
Wow. The newest version of Vivado does not like the enums as parameters. The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers. 2023-07-18 20:07:10 +00:00			`export XILINX_PART := xc7a100tcsg324-1`
			`export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1`
			`export board := ArtyA7`
Created Makefile to manage IP generation. 2021-11-30 00:32:51 +00:00
Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 16:08:35 +00:00			`# for Arty A7 and S7 boards`
Wow. The newest version of Vivado does not like the enums as parameters. The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers. 2023-07-18 20:07:10 +00:00			`all: FPGA_Arty`
Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 16:08:35 +00:00
			`# VCU 108 and VCU 118 boards`
Wow. The newest version of Vivado does not like the enums as parameters. The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers. 2023-07-18 20:07:10 +00:00			`#all: FPGA_VCU`
Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 16:08:35 +00:00
At least it simulates and gets through fpga elaboration. 2023-07-21 23:35:27 +00:00			`FPGA_Arty: PreProcessFiles IP_Arty`
Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 16:08:35 +00:00			`vivado -mode tcl -source wally.tcl 2>&1 \| tee wally.log`
Created Makefile to manage IP generation. 2021-11-30 00:32:51 +00:00
Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 16:08:35 +00:00			`FPGA_VCU: PreProcessFiles IP_VCU SDC`
Fixed bug with fpga makefile. 2022-11-07 15:20:05 +00:00			`vivado -mode tcl -source wally.tcl 2>&1 \| tee wally.log`
Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 16:05:13 +00:00
Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 16:08:35 +00:00			`IP_VCU: $(dst)/xlnx_proc_sys_reset.log \`
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 20:38:39 +00:00			`$(dst)/xlnx_ddr4-$(board).log \`
Updated to help debut Jacob's crossbar woes. 2023-04-11 19:22:42 +00:00			`$(dst)/xlnx_axi_clock_converter.log \`
Connected the axi_sdc_controller with an axi crossbar. Added an adrdec.sv to the adrdecs.sv file for the sake of the cache. Modified Uncore accordingly. 2023-01-13 19:56:01 +00:00			`$(dst)/xlnx_ahblite_axi_bridge.log \`
			`$(dst)/xlnx_axi_crossbar.log \`
			`$(dst)/xlnx_axi_dwidth_conv_32to64.log \`
Modified makefile. Added axi protocol converter IP. 2023-01-24 01:30:29 +00:00			`$(dst)/xlnx_axi_dwidth_conv_64to32.log \`
			`$(dst)/xlnx_axi_prtcl_conv.log`
Updated to help debut Jacob's crossbar woes. 2023-04-11 19:22:42 +00:00
Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 16:08:35 +00:00			`IP_Arty: $(dst)/xlnx_proc_sys_reset.log \`
			`$(dst)/xlnx_ddr3-$(board).log \`
Fixed more issues with arty a7 constarints. 2023-04-16 18:25:02 +00:00			`$(dst)/xlnx_mmcm.log \`
Created Makefile to manage IP generation. 2021-11-30 00:32:51 +00:00			`$(dst)/xlnx_axi_clock_converter.log \`
At least it simulates and gets through fpga elaboration. 2023-07-21 23:35:27 +00:00			`$(dst)/xlnx_ahblite_axi_bridge.log \`
Merge branch 'boot' into mergeBoot Merges Jacob's new sdc controller into wally. 2023-07-21 22:43:45 +00:00			`$(dst)/xlnx_axi_crossbar.log \`
			`$(dst)/xlnx_axi_dwidth_conv_32to64.log \`
			`$(dst)/xlnx_axi_dwidth_conv_64to32.log \`
			`$(dst)/xlnx_axi_prtcl_conv.log`
Created Makefile to manage IP generation. 2021-11-30 00:32:51 +00:00
Removed SDC from repo due to copy right issue. Modified fpga build flow to reference it outside the repo. 2023-01-20 20:35:46 +00:00
Removed mark_debug vivado directive from source code. Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory. 2023-01-21 01:43:18 +00:00			`PreProcessFiles:`
Updated fpga constraints. 2023-01-21 02:16:33 +00:00			`rm -rf ../src/CopiedFiles_do_not_add_to_repo/`
Removed pipelined level of hierarchy 2023-02-02 22:14:11 +00:00			`cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/`
Removed mark_debug vivado directive from source code. Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory. 2023-01-21 01:43:18 +00:00			`./insert_debug_comment.sh`

Created Makefile to manage IP generation. 2021-11-30 00:32:51 +00:00			`$(dst)/%.log: %.tcl`
			`mkdir -p IP`
			`cd IP;\`
			`vivado -mode batch -source ../$.tcl \| tee $.log`
Added make clean to fpga IP generator. 2021-11-30 00:42:28 +00:00
Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 16:05:13 +00:00			`cleanIP:`
			`rm -rf IP`

			`cleanLogs:`
			`rm -rf .jou .log`

			`cleanFPGA:`
			`rm -rf WallyFPGA.* reports sim .Xil`

			`cleanAll: cleanIP cleanLogs cleanFPGA`